VSC7125 Datasheet, PDF (7/16 Pages) Vitesse Semiconductor Corporation – 1.0625 Gbits/sec Fibre Channel Transceiver

Data Sheet
VSC7125
RCLK
RCLKN
R0:9
VITESSE
SEMICONDUCTOR CORPORATION
Figure 5: Receive Timing Waveforms
T₄
T₃
1.0625 Gbits/sec Fibre
Channel Transceiver
Data Valid
T₁
T₂
Data Valid
Data Valid
REFCLK
Figure 6: REFCLK Timing Waveforms
T_L
T_H
V_ih(min)
V_il(max)
Table 3: Reference Clock Requirements
Parameters
Description
FR
Frequency Range
Min
Max
Unit
s
Conditions
Range over which both transmit and
receive reference clocks on any link
100 110 MHz _{may be centered}
FO
Frequency Offset
Maximum frequency offset between
transmit and receive reference clocks
-200 200 ppm. _{on one link}
DC
T_RCR,T_RCF
REFCLK
Jitter
REFCLK
Jitter
REFCLK duty cycle
REFCLK rise and fall time
REFCLK Jitter Power
5MHz
∫ ^PhaseNoise
100 H z
REFCLK Jitter Power
5MHz
∫ ^PhaseNoise
100 H z
30
70
% Measured at 1.5V
—
2.0
ns. Between V_il(max) and V_ih(min)
dbc, RMS for FC compliant output
—
2
ps. _{data jitter}
dbc, RMS for 10^-12 Bit Error Ratio
—
40
ps. with zero length external path. Tested
on a sample basis
G52121-0, Rev. 4.1
4/23/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
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