VSC7125 Datasheet, PDF (12/16 Pages) Vitesse Semiconductor Corporation – 1.0625 Gbits/sec Fibre Channel Transceiver

1.0625 Gbits/sec Fibre
Channel Transceiver
VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Table 4: Pin Identification
Pin #
Name
Description
19
54, 52
31, 30
24
47
18,20,23
26
57
58
5, 10, 28,
50, 55, 59
1, 14, 15,
21, 25,
51, 56
29, 37, 42
32, 33, 46
53, 60, 63
16,17,27,
48,49,64
EWRAP
RX+, RX-
RCLK,
RCLKN
EN_CDET
COMDET
TEST1
TEST2
TEST3
TEST_4
VDDANA
VSSANA
VDDD
VSSD
VDDT
VSST
VDDP
N/C
INPUT - TTL
LOW for Normal Operation. When HIGH, an internal loopback path from the
transmitter to the receiver is enabled and the TX outputs are held HIGH.
INPUTS - Differential PECL (AC Coupling recommended)
The serial receive data inputs selected when EWRAP is LOW. Internally biased tot
VDD/2, with 3.3KΩ resistors from each input pin to VDD and GND.
OUTPUT - Complementary TTL
Recovered clocks derived from one twentieth of the RX+/- data stream. Each rising
transition of RCLK or RCLKN corresponds to a new word on R0:9.
INPUT - TTL
Enables COMDET and word resynchronization when HIGH. When LOW, keeps
current word alignment and disables COMDET.
OUTPUT - TTL
This output goes HIGH for half of an RCLK period to indicate that R0:9 contains a
Comma Character (‘0011111XXX’). COMDET will go HIGH only during a cycle
when RCLKN is rising. COMDET is enabled by EN_CDET being HIGH.
INPUT
These signals are used for factory test. For normal operation, tie to VDD.
OUTPUT
This signal is used for factory test. For normal operation, leave open.
Analog Power Supply
Analog Ground
Digital Logic Power Supply
Digital Logic Ground
TTL Output Power Supply
TTL Output Ground
PECL I/O Power Supply
No Connection. These pins are not internally connected.
Page 12
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52121-0, Rev. 4.1
4/23/98