VSC7125 Datasheet, PDF (11/16 Pages) Vitesse Semiconductor Corporation – 1.0625 Gbits/sec Fibre Channel Transceiver

VITESSE
SEMICONDUCTOR CORPORATION
Data Sheet
VSC7125
Package Pin Descriptions
Figure 10: Pin Diagram
1.0625 Gbits/sec Fibre
Channel Transceiver
V_SSD
T0
T1
T2
V_DDD
T3
T4
T5
T6
V_DDD
T7
T8
T9
V_SSD
V_SSD
N/C
63 61 59 57 55 53 51 49
1
47
3
45
5
43
7
41
9
39
11
37
13
35
15
17 19 21 23 25 27 29 31 ³³
N/C
COMDET
V_SST
R0
R1
R2
V_DDT
R3
R4
R5
R6
V_DDT
R7
R8
R9
V_SST
(Top View)
Table 4: Pin Identification
Pin #
Name
Description
2-4, 6-9,
11-13
22
62, 61
45-43, 41-
38, 36-34
T0:9
REFCLK
TX+, TX-
R0:9
INPUTS - TTL
10-bit transmit character. Parallel data on this bus is clocked in on the rising edge of
REFCLK. The data bit corresponding to T0 is transmitted first.
INPUT - TTL
This rising edge of this clock latches T0:9 into the input register. It also provides the
reference clock, at one tenth the baud rate to the PLL.
OUTPUTS - Differential PECL (AC Coupling recommended)
These pins output the serialized transmit data when EWRAP is LOW. When EWRAP
is HIGH, TX+ is HIGH and TX- is LOW.
OUTPUTS - TTL
10-bit received character. Parallel data on this bus is clocked out on the rising edges
of RCLK and RCLKN. R0 is the first bit received on RX+/RX-.
G52121-0, Rev. 4.1
4/23/98
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
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