VSC7125 Datasheet, PDF (6/16 Pages) Vitesse Semiconductor Corporation – 1.0625 Gbits/sec Fibre Channel Transceiver

VITESSE
SEMICONDUCTOR CORPORATION
1.0625 Gbits/sec Fibre
Channel Transceiver
Data Sheet
VSC7125
Table 2: Receive AC Characteristics
Parameters
T₁
T₂
T₃
T₄
Description
Data or COM_DET Valid
prior to RCLK/RCLKN
rise
Data or COM_DET Valid
after RCLK or RCLKN
rise
Deviation of RCLK
rising edge to RCLKN
rising edge delay from
nominal.
delay=
-^f---^b---^a--^u---^d-
10
±
T₃
Deviation of RCLK,
RCLKN frequency from
nominal.
f _RCLK=
-^f---^R---^E----^F---^C---^L---^K--
2
±
T
4
Min.
4.0
3.0
-500
-1.0
Max.
—
—
Units
Conditions
ns. ^{Measured between the}
1.4V point of RCLK or
RCLKN and a valid level
of R0:9. All outputs
ns. _{driving 10pF load.}
Nominal delay is 10 bit
500
ps. times. Tested on sample
basis
Whether or not locked to
1.0
% _{serial data}
T_R, T_F
R0:9, COM_DET, RCLK,
RCLKN rise and fall time
R_lat
T_LOCK
Latency from RX to R0:9
Data acquisition lock time
@ 1.0625Gb/s
Receive Data Jitter Power
Receive Data
Jitter
-2----_×-----_B----_i-1-_t--_T----_i--_m-----_e-
∫ ^PhaseNoise
100 K H z
—
15bc + 2ns
—
—
2.4
34bc + 2ns
2.4
40
ns.
Between V_il(max) and
V_ih(min), into 10 pf. load.
bc = Bit clock
ns = Nano second
µs.
8B/10B IDLE pattern.
Tested on a sample basis
dBc, RMS for l0^-12 Bit
ps. Error Ratio Tested on a
sample basis
Note: Probability of recovery for data acquisition is 95% per section 5.3 of the FC-PH rev. 4.3.
Page 6
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
G52121-0, Rev. 4.1
4/23/98