SI5857DU Datasheet, PDF (2/10 Pages) Vishay Siliconix – P-Channel 20-V (D-S) MOSFET With Schottky Diode

Si5857DU
Vishay Siliconix
THERMAL RESISTANCE RATINGS
Parameter
Symbol
Typical
Maximum
Unit
Maximum Junction-to-Ambient (MOSFET)^{b, f}
R_thJA
43
55
Maximum Junction-to-Case (Drain) (MOSFET)
Maximum Junction-to-Ambient (Schottky)^{b, g}
R_thJC
9.5
R_thJA
49
12
°C/W
61
Maximum Junction-to-Case (Drain) (Schottky)
R_thJC
13
16
Notes:
a. Package limited.
b. Surface Mounted on FR4 Board.
c. t ≤ 5 s.
d. See Solder Profile (http://www.vishay.com/doc?73257). The PowerPAK ChipFET is a leadless package. The end of the lead terminal is
exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be
guaranteed and is not required to ensure adequate bottom side solder interconnection. Rework Conditions: manual soldering with a soldering
iron is not recommended for leadless components.
e. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
f. Maximum under Steady State conditions for MOSFETS is 105 °C/W.
g. Maximum under Steady State conditions for Schottky is 110 °C/W.
SPECIFICATIONS T_J = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Static
Drain-Source Breakdown Voltage
V_DS
V_GS = 0 V, I_D = - 250 µA
V_DS Temperature Coefficient
V_GS(th) Temperature Coefficient
ΔV_DS/TJ
ΔV_GS(th)/TJ
I_D = - 250 µA
Gate-Source Threshold Voltage
V_GS(th)
V_DS = V_GS, I_D = - 250 µA
Gate-Body Leakage
I_GSS
V_DS = 0 V, V_GS = ± 12 V
Zero Gate Voltage Drain Current
I_DSS
V_DS = - 20 V, V_GS = 0 V
V_DS = - 20 V, V_GS = 0 V, T_J = 55 °C
On-State Drain Current^a
I_D(on)
V_DS ≤ - 5 V, V_GS = - 4.5 V
Drain-Source On-State Resistance^a
R_DS(on)
V_GS = - 4.5 V, I_D = - 3.6 A
V_GS = - 2.5 V, I_D = - 1 A
Forward Transconductance^a
g_fs
V_DS = - 10 V, I_D = - 3.6 A
Dynamic^b
Input Capacitance
C_iss
Output Capacitance
C_oss
V_DS = - 10 V, V_GS = 0 V, f = 1 MHz
Reverse Transfer Capacitance
C_rss
Total Gate Charge
Q_g
V_DS = - 10 V, V_GS = - 10 V, I_D = - 5 A
Gate-Source Charge
Gate-Drain Charge
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Q_gs
Q_gd
R_g
t_d(on)
t_r
t_d(off)
t_f
t_d(on)
t_r
t_d(off)
t_f
V_DS = - 10 V, V_GS = - 4.5 V, I_D = - 5 A
f = 1 MHz
V_DD = - 10 V, R_L = 2.5 Ω
I_D ≅ - 4 A, V_GEN = - 4.5 V, R_g = 1 Ω
V_DD = - 10 V, R_L = 2.5 Ω
I_D ≅ - 4 A, V_GEN = - 10 V, R_g = 1 Ω
Min. Typ. Max. Unit
- 20
- 0.6
- 20
- 19
2.6
0.048
0.081
10
- 1.5
± 100
-1
- 10
0.058
0.100
V
mV/°C
V
ns
µA
A
Ω
S
480
125
pF
90
11
17
5.5
8.5
nC
1.2
1.8
9
Ω
11
20
42
65
33
50
50
75
ns
5
10
15
25
25
40
10
20
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Document Number: 73696
S-81449-Rev. C, 23-Jun-08