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DG411LE Datasheet, PDF (10/17 Pages) Vishay Siliconix – Low Parasitic Capacitance and Leakage, Quad SPST Switches
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www.vishay.com
TEST CIRCUITS
DG411LE, DG412LE, DG413LE
Vishay Siliconix
VS
VS1
VS2
Vg
VL
VL
S
IN
GND
V+
V+
D
V-
V-
RL
300 Ω
VO
CL
35 pF
Logic
3V
Input
0V
Switch
Input*
VS
Switch
Output
Switch
Input*
0V
VO
- VS
50%
tr < 20 ns
tf < 20 ns
tON
VO
90 %
tON
90 %
CL (includes fixture and stray capacitance)
VO = VS
RL
RL + rDS(on)
Note: Logic input waveform is inverted for switches that
have the opposite logic sense control
Fig. 2 - Switching Time
VL
S1
IN1
S2
IN2
GND
V+
D1
VO1
D2
VO2
RL1
300 Ω
CL1
35 pF
V-
RL2
300 Ω
CL2
35 pF
Logic
3V
Input
0V
VS1
VO1
Switch
0V
Output
VS2
VO2
Switch
0V
Output
V-
CL (includes fixture and stray capacitance)
Fig. 3 - Break-Before-Make (DG413LE)
50 %
90 %
90 %
tD
tD
VL
Rg
VL
S
IN
3V
GND
ΔVO
V+
VO
V+
D
VO
INX
OFF
ON
OFF
CL
10 nF
V-
OFF
INX
ON
Q = ΔVO x CL
OFF
V-
INX dependent on switch configuration Input polarity determined
by sense of switch.
Fig. 4 - Charge Injection
S16-0391-Rev. A, 07-Mar-16
10
Document Number: 78091
For technical questions, contact: analogswitchsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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