TLD4012 Datasheet, PDF (8/13 Pages) Tripath Technology Inc. – ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY

Tripath Technology, Inc. - Technical Information
FUNCTIONAL DESCRIPTION
Programmable Gain
The gain of the TLD4012 is programmed by the digital inputs G3, G2, G1 and G0. The gain given below is
the gain from the input to the output of the TLD4012 with R_S=10Ω and R_LOAD=50Ω as shown in Figure 1.
Note that output voltage swing is limited for gains less than 17.8 dB (see parameter V_OUTMAX in Electrical
Characteristics).
G3 G2 G1 G0 Gain, dB Gain, V/V
0 0 0 0 12.8
4.37
0 0 0 1 13.8
4.90
0 0 1 0 14.8
5.50
0 0 1 1 15.8
6.17
0 1 0 0 16.8
6.92
0 1 0 1 17.8
7.76
0 1 1 0 18.8
8.71
0 1 1 1 19.8
9.77
1 0 0 0 20.8
10.96
1 0 0 1 21.8
12.30
1 0 1 0 22.8
13.80
1 0 1 1 23.8
15.49
1 1 0 0 24.8
17.38
1 1 0 1 25.8
19.50
1 1 1 0 26.8
21.88
1 1 1 1 27.8
24.55
Protection Circuits
The TLD4012 has built-in protection against over-temperature and over-current conditions. There are two
modes in which the fault protection circuits can operate depending on the state of the AUTO_CLR pin.
The two modes operate as follows:
1. AUTO_CLR pin is set to a logic low level - When the device goes into an over-temperature or over-
current condition, the FAULT pin is latched into a logic HIGH state indicating a fault condition. When
this occurs, the amplifier outputs enter disable mode and are in a high-impedance state provided
OUTP and OUTN are not driven externally to exceed approximately +/-2.0V_ppdiff. After the fault
condition has been removed, a logic LOW pulse must be applied to the RESETB pin for a minimum of
100 ns to reset the FAULT output to a logic low level, and re-enable the output to a normal, low
impedance mode.
2. AUTO_CLR pin is set to a logic high level - After a fault occurs and the fault condition is removed, the
device will enable the outputs, and reset the FAULT pin every 1 micro-second. In this mode the fault
latch is reset internally on power up so an external reset is not required. Note that in the case of an
over-current fault, if the cause of the over-current condition has not actually cleared, the output stage
will cycle continuously between the normal, enabled state, and the fault, or disabled state. In this
mode the FAULT output pin can cycle continuously until the cause of the fault is cleared. If this
operation is not desirable, see the “Over-current Protection” section below. If a microcontroller or DMT
processor is used to monitor the FAULT output, and to control the device, AUTO_CLR should be set
to a logic low level. Otherwise, AUTO_CLR should be set to a logic high level and the device will reset
itself on power-up and after a fault condition has been removed.
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TLD4012 – JB/Rev. 2.0a/05.02