TLD4012 Datasheet, PDF (1/13 Pages) Tripath Technology Inc. – ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY

Tripath Technology, Inc. - Technical Information
TLD4012
ADSL LINE DRIVER USING TRIPATH DIGITAL POWER
PROCESSING (DPP™) TECHNOLOGY
Technical Information
Revision 2.0a – May 2002
GENERAL DESCRIPTION
The TLD4012 is an ADSL line driver that provides very low power consumption and
low distortion in a very small package as a result of Tripath’s proprietary power
processing technology. This device accepts differential input signals from an analog
front-end (AFE), and can be used in full-rate (G.dmt), or G.lite systems. This TLD4012
offers a low power consumption of 650mW for full-rate, full-power, CO-side, FDM
(non-overlapped) transmissions.
APPLICATIONS
Full-rate or G.lite line cards
DSLAMs
DLC equipment
Central office switches
BENEFITS
Reduced line card power
Reduced system power
Increased line card density
More ports per cubic foot of system
space
Improved system performance
Simplifies thermal management on
PCB
Improved reliability
Flexible solution
FEATURES
Tripath Proprietary Power Processing technology
Very low power consumption
P_CONS(Full-rate ADSL) = 650 mW (typ)
P_CONS (G.lite) = 390 mW (typ)
Low distortion
Spurious free dynamic range = -80 dBc 26kHz to 138kHz,
R_LINE=100Ω, P_LINE=19.8dBm
Third harmonic distortion = -83 dBc at f = 100 kHz,
-82 dBc at f = 500 kHz, -63 dBc at f = 1 MHz, V_OUT = 10Vpp
(differential), 70Ω load
500 mA minimum output current into a 71Ω load
Digitally programmable gain (from 12.8 to 27.8 dB in 1 dB steps)
Low-power mode -130 mW typical (line terminated -allows
reception of incoming signals)
Disabled mode - 10 mW typical (no line termination)
Over-temperature and over-current protection with Fault output
5x5 mm 32-pin TQFP with exposed die pad
INP 3
INN 4
G3 9
G2 8
G1 7
G0 6
RESETB 14
LOPWR 15
EN_AC 1
AUTO_CLR 31
Control
&
Logic
1
VDD5 VSS5 VDD15 VSS15
25
16
21
20
Power
Processing
Block
Output
current
limit
30 FBP
23 OUTP
18 OUTN
29 FBN
27 ^REXT
11 FAULT
2
GND
5
28
GND GND
12
13
FORC_BIAS TH_FAULT
Block Diagram
EN_AC
GND
INP
INN
GND
G0
G1
G2
32 31 30 29 28 27 26 25
1
124
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
NC
OUTP
NC
VDD15
VSS15
NC
OUTN
NC
(Top View)
TLD4012 – JB/Rev. 2.0a/05.02