TLD4012 Datasheet, PDF (4/13 Pages) Tripath Technology Inc. – ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY

Tripath Technology, Inc. - Technical Information
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, T_A = 25°C, VDD5 = +5V, VSS5 = -5V, VDD15 = +15V, VSS15 = -15V. Also, see
Test/Application Circuits. See functional description for details regarding synthetic output impedance. Minimum and
maximum limits are guaranteed but may not be 100% tested.
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNITS
P_CONS1
P_CONS3
P_CONS4
P_CONS5
P_CONS6
Power Consumption
R_LOAD = 71Ω, P_OUT = 154 mW,
Full-rate, overlapped ADSL signal, line
power = 110 mW (20.4 dBm), with
synthetic output impedance (see Fig. 1)
Power Consumption, no signal
R_LOAD = 50Ω, No Input Signal,
LOPWR = Low (see Fig. 1)
Power Consumption, no signal, low power R_LOAD = 50Ω, No Input Signal,
mode
LOPWR = High (see Fig. 1)
G.Lite
R_LOAD = 71Ω, P_OUT = 58 mW,
G.Lite signal, line power = 41.6 mW
(16.2 dBm). See Fig. 1.
Disable mode
RESETB = Low
740
mW
250
mW
130
mW
390
mW
10
mW
I_DD5
Operating Current VDD5
R_LOAD = 71Ω, P_OUT = 154 mW,
47.0
mA
Full-rate, overlapped ADSL signal with
synthetic output impedance (see Fig. 1)
I_SS5
Operating Current VSS5
R_LOAD = 71Ω, P_OUT = 154 mW,
49.0
mA
Full-rate, overlapped ADSL signal with
synthetic output impedance (see Fig. 1)
I_DD15
Operating Current VDD15
R_LOAD = 71Ω, P_OUT = 154 mW,
8.0
mA
Full-rate, overlapped ADSL signal with
synthetic output impedance (see Fig. 1)
I_SS15
Operating Current VSS15
R_LOAD = 71Ω, P_OUT = 154 mW,
9.5
mA
Full-rate, overlapped ADSL signal with
synthetic output impedance (see Fig. 1)
I_q1
Quiescent Current (VDD5 and VSS5)
R_LOAD = 71Ω, No input signal, LOPWR =
21.7
mA
Low
I_q2
Quiescent Current (VDD15 and VSS15) R_LOAD = 71Ω, No input signal,
LOPWR = Low
1.1
mA
I_q1LP
Quiescent Current (VDD5 and VSS5), low R_LOAD = 71Ω, No input signal,
power mode
LOPWR = High
11.0
mA
I_q2LP
Quiescent Current (VDD15 and VSS15), R_LOAD = 71Ω, No input signal,
low power mode
LOPWR = High
0.68
mA
V_BG
Band-gap Voltage
1.28
V
V_OUTmax Differential Output Voltage, peak-to-peak Gain = 17.8 to 27.8 dB, R_LOAD = 71Ω
42
V
differential
Gain = 12.8 to 16.8 dB, R_LOAD = 71Ω
20
I_OUTmax Differential Output Current
R_LOAD = 71Ω
500
mA
I_SC
Short-circuit Output Current
R_EXT = 24kΩ
800
mA
V_IO
Differential Input Offset Voltage
600
µV
∆V_OS
V_OSHI
I_b
∆I_b
R_IDIFF
C_IDIFF
Offset Voltage Drift
Differential Output Offset Voltage
Input Bias Current
Differential Input Bias Current
Differential Input Resistance
Differential Input Capacitance
Gain = 27.8dB, EN_AC = High, 5kΩ
across INN and INP
EN_AC = Low
30
-100
0.5
0.2
800
2
µV/°C
100
mV
µA
µA
kΩ
pF
R_OUTLP
Output Resistance (while in Low-power LOPWR = High
mode)
0.5
Ω
4
TLD4012 – JB/Rev. 2.0a/05.02