TLD4012 Datasheet, PDF (10/13 Pages) Tripath Technology Inc. – ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY

Tripath Technology, Inc. - Technical Information
TEST/APPLICATION CIRCUIT
Synthesized Output Impedance
Device TLD4012 employs synthesized output impedance with a synthesis factor of 2.55. As with any line
driver, using synthesized impedance reduces power consumption, but may compromise receive-signal
strength in some applications. The 10Ω matching resistors will properly terminate a 100Ω line when a
1:1.4 transformer is used (see Figure 1). Note that, for simplicity, the hybrid and other filtering associated
with the receive signal path are not shown.
VDD5
VSS5
VDD15
VSS15
10µF 0.1 µF 10µF 0.1 µF 1µF 0.1 µF 1µF 0.1 µF
TLD4012
VDD5
25
From Analog ^CIN
Front End
C_IN
INP 3
R_IN
INN 4
Micro
Controller
G3 9
G2 8
G1 7
G0 6
RESETB 14
LOPWR 15
EN_AC 1
AUTO_CLR 31
Control
&
Logic
VSS5
16
VDD15
21
D1
VSS15
20
30 FBP
R_LOAD
Power
Processing
Block
23 OUTP
18 OUTN
29 FBN
R_S
R_S
T1
Output
current
limit
27 ^REXT
R_EXT
11 FAULT
V_LOGIC
25k
2
5
28 12
13
GND GND GND FORC_BIAS TH_FAULT
R_LINE
T1 = 1:1.4 Transformer
C_IN = 0.1 µF
R_IN = 5 kΩ
R_S = 10 Ω
R_EXT = 24 KΩ
R_LINE = 100 Ω
D1 = One UPS840 schottky diode or equivalent per 48 drivers.
Test/Application Circuit – with synthesized output impedance, TLD4012
Figure 1
10
TLD4012 – JB/Rev. 2.0a/05.02