TLD4012 Datasheet, PDF (6/13 Pages) Tripath Technology Inc. – ADSL LINE DRIVER USING TRIPATH DIGITAL POWER PROCESSING (DPP™) TECHNOLOGY

Tripath Technology, Inc. - Technical Information
PIN DESCRIPTION
PIN PIN NAME
PIN
FUNCTION
PIN DESCRIPTION
1
EN_AC
Digital input A logic high enables the input common-mode feedback loop,
and input bias current cancellation circuit
2
GND
Ground
Device Ground
3
INP
Analog input Positive terminal of differential input
4
INN
Analog input Negative terminal of differential input
5
GND
Ground
Device Ground
6
G0
Digital input Least Significant Bit of programmable gain select
7
G1
Digital input Second Least Significant Bit of programmable gain select
8
G2
Digital input Third Least Significant Bit of programmable gain select
9
G3
Digital input Most Significant Bit of programmable gain select
10
NC
No Connect
11
FAULT
Digital output A logic level high indicates that the device has an output short
(open drain) circuit or that a thermal overload has occurred
12 FORC_BIAS Digital input When set to a logic high, the device forces the bias on
regardless of fault conditions Intended for test only
13 TH_FAULT Analog input When set to a logic high, the device simulates a thermal fault.
Intended for test only
14 RESETB
Digital input When AUTO_CLR is set to a logic low, a logic low pulse on
RESETB clears the internal Fault latch; otherwise, connect
RESETB to VDD5; Logic low puts device in disabled mode
15
LOPWR
Digital input When set to logic high, the device goes into low-power mode
16
VSS5
Power supply Negative 5V supply voltage
17
NC
No Connect
18
OUTN
Analog output Negative terminal of differential output
19
NC
No Connect
20
VSS15
Power supply Negative 15V supply voltage
21
VDD15
Power supply Positive 15V supply voltage
22
NC
No Connect
23
OUTP
Analog output Positive terminal of differential output
24
NC
No Connect
25
VDD5
Power supply Positive 5V supply voltage
26
NC
No Connect
27
R_EXT
Analog input Sets over-current limit
28
GND
Ground
Device Ground
29
FBN
Analog input Feedback path for synthesized output impedance
30
FBP
Analog input Feedback path for synthesized output impedance
31 AUTO_CLR Digital input A logic high forces an immediate reset of the fault latch when
RESETB is a logic high. A logic low requires that the RESETB
pin be pulsed low to reset the fault latch
32
NC
No Connect
EP Exposed pad
Substrate
Exposed pad at underside of device; must be connected to
VSS15. Internally connected to the substrate.
6
TLD4012 – JB/Rev. 2.0a/05.02