THM72V2010AG Datasheet, PDF (9/30 Pages) Toshiba Semiconductor – 2,097,152 WORDS X 72 BIT DYNAMIC RAM MODULE

DM16050295
Standard DRAM
THM72V2010AG/ATG-60/70
Notes:
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
2. All voltages are referenced to V_SS.
3. I_CC1, I_CC3, I_CC4, I_CC6 depend on cycle rate.
4. I_CC1, I_CC4 depend on output loading. Specified values are obtained with the output open.
5. Address can be changed one or less while RAS=V_IL. In case of I_CC4, it can be changed once or less during a fast page mode cycle (t_PC).
6. An initial pause of 500µs is required after power-up followed by 8 RAS only refresh cycles before proper device operation is achieved. When the internal
refresh counter is used, a minimum of 8 CAS before RAS refresh cycles instead of 8 RAS only refresh cycles are required.
7. AC measurements assume t_T=5ns.
8. V_IH (min.) and V_IL (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between V_IH and V_IL.
9. This parameter is measured with a load equivalent to 100pF and at V_OH=2.0V (I_OUT= -2mA), V_OL=2.0V (I_OUT=2mA).
10. t_OFF (max.) and t_OEZ (max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels.
11. Either t_RCH or t_RRH must be satisfied for a read cycle.
12. These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in Read-Modify-Write cycles.
13. t_WCS, t_RWD, t_CWD, t_AWD and t_CPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t_WCS
≥t_WCS (min.), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) through the entire cycle; If t_RWD≥t_RWD (min.),
t_CWD≥t_CWD (min.), t_AWD≥t_AWD (min.) and t_CPWD≥t_CPWD (min.) (Fast Page Mode), the cycle is a Read-Modify-Write cycle and the data out will contain data
read from the selected cell: If neither of the above sets of conditions are satisfied, the condition of the data out (at access time) is indeterminate.
14. Operation within the t_RCD (max.) limit insures that t_RAC can be met. t_RCD (max.) is specified as a reference point only: If t_RCD is greater than the specified
t_RCD (max.) limit, then access time is controlled by t_CAC.
15. Operation within the t_RAD (max.) limit insures that t_RAC (max.) can be met. t_RAD (max.) is specified as a reference point only: If t_RAD is greater than the
specified t_RAD (max.) limit, then access time is controlled by t_AA.27
PRELIMINARY
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