THM72V2010AG Datasheet, PDF (27/30 Pages) Toshiba Semiconductor – 2,097,152 WORDS X 72 BIT DYNAMIC RAM MODULE

DM16050295
Standard DRAM
THM72V2010AG/ATG-60/70
Test Mode
The TC51V17800ANJ/ANT is the RAM organized as 2,097,152 words by 8 bits, it is internally organized as 1,048,576 words by
16 bits. In “Test Mode”, data are written into 16 sectors in parallel by using only I/O1. A9C is not used. If, upon reading, 16 bits are
equal (all “1”’s or “0”’s), the I/O8 pin indicates a “1”. If they were not equal, the I/O8 pin would indicate a “0”. Other I/O pins (I/O1 ~
7) always indicate a “1” a during test mode read cycle. Figure 1 shows the block diagram of TC51V17800ANJ/ANT. In “Test
Mode”, the 2Mx8 DRAM can be tested as if it were a 1Mx16 DRAM.
“WE, CAS Before RAS Refresh Cycle” puts the device into “Test Mode”, and “CAS Before RAS Refresh Cycle” or “RAS Only
Refresh Cycle” puts it back into “Normal Mode”. In the Test Mode, “WE, CAS Before RAS Refresh Cycle” performs the refresh oper-
ation with the internal refresh address counter. The “Test Mode” function reduces test times (1/2 in case of N test pattern).
PRELIMINARY
TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
27