TC55NEM216AFTN55 Datasheet, PDF (8/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55NEM216AFTN55,70
Note:
(1)
(2)
(3)
(4)
(5)
R/W remains HIGH for the read cycle.
If CE (or UB or LB ) goes LOW coincident with or after R/W goes LOW, the outputs will remain at
high impedance.
If CE (or UB or LB ) goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at
high impedance.
If OE is HIGH during the write cycle, the outputs will remain at high impedance.
Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be
applied.
DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C)
SYMBOL
PARAMETER
MIN
V_DH
I_DDS2
t_CDR
t_R
Data Retention Supply Voltage
2.0
Standby Current
Ta = −40~40°C

Ta = −40~85°C

Chip Deselect to Data Retention Mode Time
0
Recovery Time
5
TYP





MAX
5.5
3
20


UNIT
V
µA
ns
ms
CE _{CONTROLLED DATA RETENTION MODE}
V_DD
V_DD
4.5 V
DATA RETENTION MODE
V_IH
CE
GND
(See Note 1)
t_CDR
V_DD − 0.2 V
UB , LB CONTROLLED DATA RETENTION MODE ^{(See Note 2)}
V_DD
V_DD
4.5 V
DATA RETENTION MODE
(See Note 1)
t_R
V_IH
UB , LB
GND
(See Note 3)
t_CDR
V_DD − 0.2 V
(See Note 3)
t_R
2002-07-04 8/11