TC55NEM216AFTN55 Datasheet, PDF (5/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55NEM216AFTN55,70
AC CHARACTERISTICS AND OPERATING CONDITIONS
(Ta = −40° to 85°C, V_DD = 5 V ± 10%)
READ CYCLE
SYMBOL
PARAMETER
t_RC
t_ACC
t_CO
t_OE
t_BA
t_COE
t_OEE
t_BE
t_OD
t_ODO
t_BD
t_OH
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control Low to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold Time
TC55NEM216AFTN
55
70
MIN MAX MIN MAX
55

70


55

70

55

70

30

35

55

70
5

5

0

0

5

5


25

30

25

30

25

30
10

10

UNIT
ns
WRITE CYCLE
TC55NEM216AFTN
SYMBOL
PARAMETER
55
70
UNIT
MIN MAX MIN MAX
t_WC
Write Cycle Time
55

70

t_WP
Write Pulse Width
40

50

t_CW
Chip Enable to End of Write
45

55

t_BW
Data Byte Control to End of Write
45

55

t_AS
Address Setup Time
t_WR
Write Recovery Time
0

0

ns
0

0

t_ODW
R/W Low to Output High-Z

25

30
t_OEW
R/W High to Output Active
0

0

t_DS
Data Setup Time
25

30

t_DH
Data Hold Time
0

0

Note: t_OD, t_ODO, t_BD and t_ODW are specified in time when an output becomes high impedance, and are not judged depending on
an output voltage level.
AC TEST CONDITIONS
PARAMETER
Input pulse level
t_R, t_F
Timing measurements
Reference level
Output load
TEST CONDITION
0.4 V, 2.4 V
5 ns
1.5 V
1.5 V
100 pF + 1 TTL Gate
2002-07-04 5/11