TC55NEM216AFTN55 Datasheet, PDF (1/11 Pages) Toshiba Semiconductor – TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TC55NEM216AFTN55,70
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
262,144-WORD BY 16-BIT FULL CMOS STATIC RAM
DESCRIPTION
The TC55NEM216AFTN is a 4,194,304-bit static random access memory (SRAM) organized as 262,144 words by
16 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 5V ±
10% power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3
mA/MHz (typ) and a minimum cycle time of 55 ns. It is automatically placed in low-power mode at 1 µA standby
current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device
and for data retention control, and output enable ( OE ) provides fast memory access. Data byte control pin ( LB ,
UB ) provides lower and upper byte access. This device is well suited to various microprocessor system applications
where high speed, low power and battery backup are required. And, with a guaranteed operating extreme
temperature range of −40° to 85°C, the TC55NEM216AFTN can be used in environments exhibiting extreme
temperature conditions. The TC55NEM216AFTN is available in a plastic 54-pin thin-small-outline package
(TSOP).
FEATURES
• Low-power dissipation
Operating: 15 mW/MHz (typical)
• Single power supply voltage of 5 V ± 10%
• Power down features using CE
• Data retention supply voltage of 2.0 to 5.5 V
• Direct TTL compatibility for all inputs and outputs
• Wide operating temperature range of −40° to 85°C
• Standby Current (maximum): 20 µA
• Access Times (maximum):
TC55NEM216AFTN
55
70
Access Time
55 ns
70 ns
CE Access Time
55 ns
70 ns
OE Access Time
30 ns
35 ns
• Package:
TSOP II54-P-400-0.80
(Weight: g typ)
PIN ASSIGNMENT (TOP VIEW)
54 PIN TSOP
NC 1
A3 2
A2 3
A1 4
A0 5
I/O16 6
I/O15 7
VDD 8
GND 9
I/O14 10
I/O13 11
UB ¹²
CE ¹³
OP 14
R/W 15
I/O12 16
I/O11 17
GND 18
VDD 19
I/O10 20
I/O9 21
NC 22
A17 23
A16 24
A15 25
A14 26
A13 27
54 A4
53 A5
52 A6
51 A7
50 NC
49 I/O1
48 I/O2
47 VDD
46 GND
45 I/O3
44 I/O4
43 _LB
42 _OE
41 OP
40 NC
39 I/O5
38 I/O6
37 GND
36 VDD
35 I/O7
34 I/O8
33 A8
32 A9
31 A10
30 A11
29 A12
28 NC
PIN NAMES
A0~A17 Address Inputs
CE
Chip Enable
R/W
Read/Write Control
OE
Output Enable
LB , UB Data Byte Control
I/O1~I/O16 Data Inputs/Outputs
V_DD
GND
Power (+5 V)
Ground
NC
No Connection
OP*
Option
*: OP pin must be open or connected to GND.
2002-07-04 1/11