SSM6L14FE Datasheet, PDF (3/9 Pages) Toshiba Semiconductor – Power Management Switch Applications

Q1 Switching Time Test Circuit
(a) Test Circuit
(b) V_IN
SSM6L14FE
2.5 V
IN
0
10 μs
V_DD = 10 V
R_G = 4.7 Ω
Duty ≤ 1%
V_IN: t_r, t_f < 5 ns
Common Source
Ta = 25°C
OUT
V_DD
(c) V_OUT
2.5 V
0V
V_DD
V_{DS (ON)}
10%
90%
90%
10%
t_r
t_f
t_on
t_off
Q2 Switching Time Test Circuit
(a) Test Circuit
0
IN
−2.5V
10 μs
V_DD =− 10 V
R_G = 50 Ω
Duty ≤ 1%
V_IN: t_r, t_f < 5 ns
Common Source
Ta = 25°C
OUT
R_L
V_DD
(b) V_IN
0V
(c) V_OUT
−2.5 V
V_{DS (ON)}
V_DD
90%
10%
90%
10%
t_r
t_f
t_on
t_off
Q1 Usage Considerations
Let V_th be the voltage applied between gate and source that causes the drain current (I_D) to below (1 mA for the Q1 of
the SSM6L14FE). Then, for normal switching operation, V_GS(on) must be higher than V_th, and V_GS(off) must be lower
than V_th. This relationship can be expressed as: V_GS(off) < V_th < V_GS(on).
Take this into consideration when using the device.
Q2 Usage Considerations
Let V_th be the voltage applied between gate and source that causes the drain current (I_D) to below (−1 mA for the Q2
of the SSM6L14FE). Then, for normal switching operation, V_GS(on) must be higher than V_th, and V_GS(off) must be lower
than V_th. This relationship can be expressed as: V_GS(off) < V_th < V_GS(on).
Take this into consideration when using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance R_{th (ch-a)} and power dissipation P_D vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration
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2010-03-25