MAX11311 Datasheet, PDF (49/51 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

MAX11311
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
Configuration Software Output File (continued)
Name
port_cfg_p8
port_cfg_p9
port_cfg_p10
port_cfg_p11
reserved_31
reserved_32
reserved_33
reserved_60
reserved_61
dac_data_port_p0
dac_data_port_p1
dac_data_port_p2
dac_data_port_p3
dac_data_port_p4
dac_data_port_p5
reserved_68
reserved_69
reserved_6A
dac_data_port_p6
dac_data_port_p7
dac_data_port_p8
dac_data_port_p9
dac_data_port_p10
dac_data_port_p11
reserved_71
reserved_72
reserved_73
Address
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
Value
0x0000
0x1000
0x4009
0x5100
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0666
0x0000
0x0000
0x0000
0x0666
0x0000
0x0000
0x0666
0x0666
0x0000
0x0000
0x0000
0x0000
Description
Configuration register for PIXI port P8 Software Controlled Analog Switch
Configuration register for PIXI port P9 Level Translator
Configuration register for PIXI port P10 Level Translator
Configuration register for PIXI port P11 DAC
Configuration register for (reserved) N.C.
Configuration register for (reserved) N.C.
Configuration register for (reserved) N.C.
DAC data register for (reserved) N.C.
DAC data register for (reserved) N.C.
DAC data register for PIXI port P0 Single Ended ADC
DAC data register for PIXI port P1 DAC
DAC data register for PIXI port P2 Differential ADC (+)
DAC data register for PIXI port P3 Differential ADC (-)
DAC data register for PIXI port P4 DAC with ADC Monitoring
DAC data register for PIXI port P5 GPI
DAC data register for (reserved) N.C.
DAC data register for (reserved) N.C.
DAC data register for (reserved) N.C.
DAC data register for PIXI port P6 GPO
DAC data register for PIXI port P7 Software Controlled Analog Switch
DAC data register for PIXI port P8 Software Controlled Analog Switch
DAC data register for PIXI port P9 Level Translator
DAC data register for PIXI port P10 Level Translator
DAC data register for PIXI port P11 DAC
DAC data register for (reserved) N.C.
DAC data register for (reserved) N.C.
DAC data register for (reserved) N.C.
Layout, Grounding, Bypassing
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the MAX11311 package. Noise in AVDD,
AGND, AVDDIO, AVSSIO, ADC_REF_INT, and DAC_
REF affects the device performance. Bypass AVDD,
DVDD, AVDDIO, and AVSSIO to ground with 0.1µF and
10µF bypass capacitors. Bypass ADC_INT_REF and
DAC_REF to ground with capacitors whose values are
shown in the REF Electrical Specifications table. Place
the bypass capacitors as close as possible to the respective
pins and minimize capacitor lead and trace lengths for
best supply-noise rejection. For optimum heat dissipation,
connect the exposed pad (EP) to a large copper area,
such as a ground plane.
www.maximintegrated.com
Maxim Integrated │  49