MAX11311 Datasheet, PDF (24/51 Pages) Maxim Integrated Products – PIXI, 12-Port Programmable Mixed-Signal I/O with 12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO

MAX11311
PIXI, 12-Port Programmable Mixed-Signal I/O with
12-Bit ADC, 12-Bit DAC, Analog Switches, and GPIO
In addition to port-specific DAC data registers, the host
can also use the same data for all DAC-related ports
using one of two preset DAC data registers.
All DAC output drivers are protected by overcurrent limit
circuitry. In case of overcurrent, the MAX11311 generates
an interrupt. Detailed status registers are offered to the
host to determine which ports are current limited.
General-Purpose Input and Output
Each PIXI port can be configured as a GPI or a GPO. The
GPI threshold (Figure 8) is adjusted by setting the DAC
data register of that GPI port to the corresponding voltage.
If the DAC data register is set at 0x0FFF, the GPI threshold
is the DAC reference voltage. The amplitude of the input
signal must be contained within 0V to V_AVDD. The GPI-
configured port can be set to detect rising edges, falling
edges, either rising or falling edges, or none.
When a port is configured as GPO (Figure 9), the amplitude
of its logic-one level is set by its DAC data register. If the
DAC data register is set at 0x0FFF, the GPO logic-one
level is four times the DAC reference voltage. The logic-
zero level is always 0V. The host can set the logic state
of GPO-configured ports through the corresponding GPO
data registers.
Figure 8. GPI Mode
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
SEQUENCER
PORT
GPI
±30mV HYSTERESIS
DAC
DIGITAL
CORE
SPI
SERIAL
INTERFACE
INT
SERIAL
INTERFACE
SPI
Figure 9. GPO Mode
DAC_REF INTERNAL OR
EXTERNAL FOR ALL PORTS
DAC
DIGITAL
CORE
SEQUENCER
SCALING
BLOCK
GPO
PORT
CURRENT LIMIT at 50mA
INT
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