TM4C129CNCZAD Datasheet, PDF (995/1772 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129CNCZAD Microcontroller
Register 40: AES DMA Raw Interrupt Status (AES_DMARIS), offset 0x024
The AES DMA Raw Interrupt Status (AES_DMARIS) register contains the raw interrupt status. If
any of these bits read 1, the processor is interrupted if the corresponding masked interrupt status
bit is set to '1.'
AES DMA Raw Interrupt Status (AES_DMARIS)
Base 0x4403.0000
Offset 0x024
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
DOUT
DIN
COUT
CIN
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:4
3
Name
reserved
DOUT
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0
Data Out DMA Done Raw Interrupt Status
Value Description
0 No Interrupt.
1 The µDMA has written the last word of the process result and
an interrupt has been triggered and is pending.
2
DIN
RW
0
Data In DMA Done Raw Interrupt Status
Value Description
0 No Interrupt.
1 The µDMA has written the last word of input data to the internal
FIFO of the engine and an interrupt has been triggered and is
pending.
1
COUT
RW
0
Context Out DMA Done Raw Interrupt Status
Value Description
0 No Interrupt.
1 The µDMA has completed the output context read from the
internal register and an interrupt has been triggered and is
pending.
June 18, 2014
995
Texas Instruments-Production Data