TM4C129CNCZAD Datasheet, PDF (556/1772 Pages) Texas Instruments – Tiva Microcontroller

Hibernation Module
Bit/Field
4
3
2
1
0
Name
WC
EXTW
LOWBAT
reserved
RTCALT0
Type
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
Description
Write Complete/Capable Masked Interrupt Status
Value Description
0 The WRC bit has not been set or the interrupt is masked.
1 An unmasked interrupt was signaled due to the WRC bit being
set.
This bit is cleared by writing a 1 to the WC bit in the HIBIC register.
External Wake-Up Masked Interrupt Status
Value Description
0 An external wake-up interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a WAKE pin
assertion.
This bit is cleared by writing a 1 to the EXTW bit in the HIBIC register.
Low Battery Voltage Masked Interrupt Status
Value Description
0 A low-battery voltage interrupt has not occurred or is masked.
1 An unmasked interrupt was signaled due to a low-battery voltage
condition.
This bit is cleared by writing a 1 to the LOWBAT bit in the HIBIC register.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RTC Alert 0 Masked Interrupt Status
Note: The MIS may apply to either the RTC or calendar block
depending on which is enabled.
Value Description
0 An RTC or calendar match interrupt has not occurred or is
masked.
1 An unmasked interrupt was signaled due to an RTC or calendar
match.
This bit is cleared by writing a 1 to the RTCALT0 bit in the HIBIC register.
556
June 18, 2014
Texas Instruments-Production Data