TM4C129CNCZAD Datasheet, PDF (13/1772 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129CNCZAD Microcontroller
List of Figures
Figure 1-1.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 3-1.
Figure 3-2.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure 4-4.
Figure 4-5.
Figure 5-1.
Figure 5-2.
Figure 5-3.
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 7-1.
Figure 7-2.
Figure 7-3.
Figure 7-4.
Figure 7-5.
Figure 7-6.
Figure 7-7.
Figure 7-8.
Figure 8-1.
Figure 8-2.
Figure 8-3.
Figure 8-4.
Figure 8-5.
Figure 8-6.
Figure 8-7.
Figure 9-1.
Figure 9-2.
Figure 9-3.
Figure 9-4.
Figure 9-5.
Figure 9-6.
Figure 10-1.
Figure 10-2.
Figure 10-3.
Tiva^™ TM4C129CNCZAD Microcontroller High-Level Block Diagram ...................... 55
CPU Block Diagram ............................................................................................. 83
TPIU Block Diagram ............................................................................................ 84
Cortex-M4F Register Set ...................................................................................... 87
Bit-Band Mapping .............................................................................................. 112
Data Storage ..................................................................................................... 113
Vector Table ...................................................................................................... 121
Exception Stack Frame ...................................................................................... 124
SRD Use Example ............................................................................................. 142
FPU Register Bank ............................................................................................ 145
JTAG Module Block Diagram .............................................................................. 210
Test Access Port State Machine ......................................................................... 214
IDCODE Register Format ................................................................................... 220
BYPASS Register Format ................................................................................... 220
Boundary Scan Register Format ......................................................................... 220
Basic RST Configuration .................................................................................... 226
External Circuitry to Extend Power-On Reset ....................................................... 226
Reset Circuit Controlled by Switch ...................................................................... 226
Power Architecture ............................................................................................ 232
Main Clock Tree ................................................................................................ 235
Module Clock Selection ...................................................................................... 243
Hibernation Module Block Diagram ..................................................................... 522
Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 526
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 526
Using a Regulator for Both V_DD and V_BAT ............................................................ 527
Counter Behavior with a TRIM Value of 0x8002 ................................................... 531
Counter Behavior with a TRIM Value of 0x7FFC .................................................. 531
Tamper Block Diagram ....................................................................................... 531
Tamper Pad with Glitch Filtering ......................................................................... 532
Internal Memory Block Diagram .......................................................................... 590
Flash Memory Configuration ............................................................................... 594
Single 256-Bit Prefetch Buffer Set ....................................................................... 595
Four 256-Bit Prefetch Buffer Configuration .......................................................... 595
Single Cycle Access, 0 Wait States ..................................................................... 596
Prefetch Fills from Flash ..................................................................................... 597
Mirror Mode Function ......................................................................................... 598
μDMA Block Diagram ......................................................................................... 668
Example of Ping-Pong μDMA Transaction ........................................................... 675
Memory Scatter-Gather, Setup and Configuration ................................................ 677
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 678
Peripheral Scatter-Gather, Setup and Configuration ............................................. 680
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 681
Digital I/O Pads ................................................................................................. 738
Analog/Digital I/O Pads ...................................................................................... 739
GPIODATA Write Example ................................................................................. 740
June 18, 2014
13
Texas Instruments-Production Data