TM4C129CNCZAD Datasheet, PDF (742/1772 Pages) Texas Instruments – Tiva Microcontroller

General-Purpose Input/Outputs (GPIOs)
an ADC conversion is initiated. See page 1201. Note that whether the GPIO is configured to trigger
on edge events or level events, a single-clock ADC trigger pulse is created in either event. Thus,
when a level event is selected, the ADC sample sequence will run only one time and multiple sample
sequences will not be executed if the level remains the same. It is recommended that edge events
be used as ADC trigger source.
Note that if the Port B GPIOADCCTL register is cleared, PB4 can still be used as an external trigger
for the ADC. This is a legacy mode which allows code written for previous devices to operate on
this microcontroller.
10.3.2.3
μDMA Trigger Source
Any GPIO pin can be configured to be an external trigger for the μDMA using the GPIO DMA Control
(GPIODMACTL) register. If any GPIO is configured as a non-masked interrupt pin (the appropriate
bit of GPIOIM is set), a dma_req signal is sent to the µDMA. If the μDMA is configured to start a
transfer based on the GPIO signal, a transfer is initiated. When transfer is complete, the dma_done
signal is sent from the µDMA to the GPIO and is reported as a DMA (done) interrupt in the GPIORIS
register.
10.3.2.4
HIB Wake Source
GPIO pins K[7:4] on Port K can be configured as an external wake source for the hibernation (HIB)
module. The pins can be configured in the following way:
1. Write 0x0000.0040 to the HIBCTL register at offset 0x010 to enable 32.768-kHz Hibernation
oscillator.
2. Write any data to be retained during power cut to the HIBDATA register at offsets 0x030-0x06F.
3. Configure the GPIOWAKEPEN and GPIOWAKELVL registers at offsets 0x540 and 0x544 in
the GPIO module. Enable the I/O wake pad configuration by writing 0x0000.0001 to the HIBIO
register at offset 0x010.
4. When the IOWRC bit in the HIBIO register is read as 1, write 0x0000.0000 to the HIBO register
to lock the current pad configuration so that any other writes to the GPIOWAKEPEN and
GPIOWAKELVL register will be ignored.
5. The hibernation sequence may be initiated by writing 0x0000.0052 to the HIBCTL register.
The GPIOWAKESTAT register at offset 0x548 can be read to determine which port caused a wake
pin assertion.
10.3.3
Mode Control
The GPIO pins can be controlled by either software or hardware. Software control is the default for
most signals and corresponds to the GPIO mode, where the GPIODATA register is used to read
or write the corresponding pins. When hardware control is enabled via the GPIO Alternate Function
Select (GPIOAFSEL) register (see page 762), the pin state is controlled by its alternate function
(that is, the peripheral).
Further pin muxing options are provided through the GPIO Port Control (GPIOPCTL) register which
selects one of several peripheral functions for each GPIO. For information on the configuration
options, refer to Table 28-5 on page 1693.
Note: If any pin is to be used as an ADC input, the appropriate bit in the GPIOAMSEL register
must be set to disable the analog isolation circuit.
742
June 18, 2014
Texas Instruments-Production Data