TM4C129CNCZAD Datasheet, PDF (1105/1772 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C129CNCZAD Microcontroller
Register 7: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C
This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or
not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its
corresponding bit in GPTMICR.
Note:
The state of the GPTMRIS register is not affected by disabling and then re-enabling the
timer using the TnEN bits in the GPTM Control (GPTMCTL) register. If an application
requires that all or certain status bits should not carry over after re-enabling the timer, then
the appropriate bits in the GPTMRIS register should be cleared using the GPTMICR register
prior to re-enabling the timer. If this is not done, any status bits set in the GPTMRIS register
and unmasked in the GPTMIMR register generate an interrupt once the timer is re-enabled.
GPTM Raw Interrupt Status (GPTMRIS)
16/32-bit Timer 0 base: 0x4003.0000
16/32-bit Timer 1 base: 0x4003.1000
16/32-bit Timer 2 base: 0x4003.2000
16/32-bit Timer 3 base: 0x4003.3000
16/32-bit Timer 4 base: 0x4003.4000
16/32-bit Timer 5 base: 0x4003.5000
16/32-bit Timer 6 base: 0x400E.0000
16/32-bit Timer 7 base: 0x400E.1000
Offset 0x01C
Type RO, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Type
Reset
15
14
reserved
RO
RO
0
0
13
12
11
10
9
8
DMABRIS reserved TBMRIS CBERIS CBMRIS TBTORIS
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
7
6
reserved
RO
RO
0
0
5
4
3
2
1
0
DMAARIS TAMRIS RTCRIS CAERIS CAMRIS TATORIS
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
Bit/Field
31:14
13
Name
reserved
DMABRIS
Type
RO
RO
Reset
0x0000
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
GPTM Timer B DMA Done Raw Interrupt Status
Value Description
0 The Timer B DMA transfer has not completed.
1 The Timer B DMA transfer has completed.
12
reserved
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2014
Texas Instruments-Production Data
1105