TMS320VC5504_13 Datasheet, PDF (99/123 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5504
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SPRS609B – JUNE 2009 – REVISED JANUARY 2010
Table 6-33. Switching Characteristics Over Recommended Operating Conditions for I2S Output
[I/O = 1.8 V] (see Figure 6-25)
NO.
PARAMETER
1 t_c(CLK)
Cycle time, I2S_CLK
MASTER
SLAVE
CV_DD = 1.05 V CV_DD = 1.3 V CV_DD = 1.05 V CV_DD = 1.3 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
50 or
2P ^{(1) (2)}
40 or
2P ⁽¹⁾
(2)
50 or
2P^{(1) (2)}
40 or
2P ⁽¹⁾
(2)
ns
2
t_w(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 0)
25
20
t_w(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 1)
25
20
3
t_w(CLKL)
Pulse duration, I2S_CLK low (CLKPOL = 0)
25
20
t_w(CLKH)
Pulse duration, I2S_CLK high (CLKPOL = 1)
25
20
t_dmax(CLKL- Output Delay time, I2S_CLK low to I2S_DX
4 ^DXV)
valid (CLKPOL = 0)
t_dmax(CLKH- Output Delay time, I2S_CLK high to I2S_DX
DXV)
valid (CLKPOL = 1)
19
14
19
14
t_oh(DXV-CLKH)
Output Hold time, I2S_CLK high to I2S_DX
invalid (CLKPOL = 0)
0
0
5
t_oh(DXV-
CLKL)
Output Hold time, I2S_CLK low to I2S_DX
invalid (CLKPOL = 1)
0
0
t_dmax(CLKL- Delay time, I2S_CLK low to I2S_FS valid
6 ^FSV)
(CLKPOL = 0)
t_dmax(CLKH- Delay time, I2S_CLK high to I2S_FS valid
FSV)
(CLKPOL = 1)
14
14
14
14
(1) P = SYSCLK period in ns. For example, when running parts at 100 MHz, use P = 10 ns.
(2) Use whichever value is greater.
25
25
25
25
15
15
0
0
–
–
20
ns
20
ns
20
ns
20
ns
12 ns
12 ns
0
ns
0
ns
– ns
– ns
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Peripheral Information and Electrical Specifications
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