TMS320VC5504_13 Datasheet, PDF (115/123 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5504
www.ti.com
SPRS609B – JUNE 2009 – REVISED JANUARY 2010
6.18.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-44. Timing Requirements for GPIO Inputs⁽¹⁾ (see Figure 6-31)
CV_DD = 1.05 V
NO.
CV_DD = 1.3 V
UNIT
MIN MAX
1 t_w(ACTIVE)
2 t_w(INACTIVE)
Pulse duration, GPIO input/external interrupt pulse active
Pulse duration, GPIO input/external interrupt pulse inactive
2C ^{(1) (2)}
ns
C ^{(1) (2)}
ns
(1) The pulse width given is sufficient to get latched into the GPIO_IFR register and to generate an interrupt. However, if a user wants to
have the device recognize the GPIO changes through software polling of the GPIO Data In (GPIO_DIN) register, the GPIO duration
must be extended to allow the device enough time to access the GPIO register through the internal bus.
(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
Table 6-45. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-31)
NO.
PARAMETER
CV_DD = 1.05 V
CV_DD = 1.3 V
UNIT
MIN MAX
3
t_w(GPOH)
4
t_w(GPOL)
Pulse duration, GP[x] output high
Pulse duration, GP[x] output low
3C ^{(1) (2)}
ns
3C ^{(1) (2)}
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C = SYSCLK period in ns. For example, when running parts at 100 MHz, use C = 10 ns.
GP[x] Input
(With IOINTEDGy = 0)
GP[x] Input
(With IOINTEDGy = 1)
GP[x] Output
2
1
2
1
4
3
Figure 6-31. GPIO Port Timing
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Peripheral Information and Electrical Specifications 115
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