TMS320VC5504_13 Datasheet, PDF (90/123 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5504
SPRS609B – JUNE 2009 – REVISED JANUARY 2010
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SDA
SCL
11
8
4
10
6
5
1
3
12
7
9
14
13
3
2
Stop Start
Repeated
Start
Stop
Figure 6-22. I2C Receive Timings
Table 6-22. Switching Characteristics for I2C Timings⁽¹⁾ (see Figure 6-23)
NO.
PARAMETER
16
t_c(SCL)
Cycle time, SCL
17
t_d(SCLH-SDAL)
Delay time, SCL high to SDA low (for a repeated START
condition)
18
t_d(SDAL-SCLL)
Delay time, SDA low to SCL low (for a START and a repeated
START condition)
19
t_w(SCLL)
Pulse duration, SCL low
20
t_w(SCLH)
Pulse duration, SCL high
21 t_d(SDAV-SCLH) Delay time, SDA valid to SCL high
22 t_v(SCLL-SDAV) Valid time, SDA valid after SCL low
23
t_w(SDAH)
Pulse duration, SDA high between STOP and START
conditions
24
t_r(SDA)
Rise time, SDA⁽²⁾
CV_DD = 1.05 V
CV_DD = 1.3 V
STANDARD
MODE
FAST MODE
MIN MAX
MIN MAX
10
2.5
UNIT
µs
4.7
0.6
µs
4
4.7
4
250
0
4.7
1000
0.6
1.3
0.6
100
0
1.3
20 + 0.1C_b
(1)
µs
µs
µs
ns
0.9 µs
µs
300 ns
25
t_r(SCL)
Rise time, SCL⁽²⁾
1000
20 + 0.1C_b
(1)
300 ns
26
t_f(SDA)
Fall time, SDA⁽²⁾
300
20 + 0.1C_b
(1)
300 ns
27
t_f(SCL)
Fall time, SCL⁽²⁾
300
20 + 0.1C_b
(1)
300 ns
28 t_d(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition)
4
0.6
µs
29 C_p
Capacitance for each I2C pin
10
10 pF
(1) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) The rise/fall times are measured at 30% and 70% of DV_DDIO. The fall time is only slightly influenced by the external bus load (C_b) and
external pullup resistor. However, the rise time (t_r) is mainly determined by the bus load capacitance and the value of the pullup resistor.
The pullup resistor must be selected to meet the I2C rise and fall time values specified.
90
Peripheral Information and Electrical Specifications
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