TDA2EG Datasheet, PDF (98/393 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 23mm Package (ABC Package) Silicon Revision 2.0

TDA2EG
SPRS958B – MARCH 2016 – REVISED JANUARY 2017
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Table 4-13. SPI Signal Descriptions (continued)
SIGNAL NAME
spi2_sclk⁽¹⁾
DESCRIPTION
SPI2 Clock
TYPE
IO
BALL
A26
spi2_d1
SPI2 Data. Can be configured as either MISO or MOSI.
IO
B22
spi2_d0
SPI2 Data. Can be configured as either MISO or MOSI.
IO
G17
spi2_cs0
SPI2 Chip Select
IO
B24
spi2_cs1
SPI2 Chip Select
IO
A22
spi2_cs2
SPI2 Chip Select
IO
B21
spi2_cs3
SPI2 Chip Select
IO
B20
Serial Peripheral Interface 3
spi3_sclk⁽¹⁾
SPI3 Clock
IO
AC4 / B12 / C18 /
E11 / V2
spi3_d1
SPI3 Data. Can be configured as either MISO or MOSI.
IO
A11 / A21 / AC7 /
B10 / Y1
spi3_d0
SPI3 Data. Can be configured as either MISO or MOSI.
IO
AC6 / B13 / C11 /
G16 / W9
spi3_cs0
SPI3 Chip Select
IO
A12 / AC9 / D11 /
D17 / V9
spi3_cs1
SPI3 Chip Select
IO
AC3 / B11 / E14
spi3_cs2
SPI3 Chip Select
IO
F11
spi3_cs3
SPI3 Chip Select
IO
A10
Serial Peripheral Interface 4
spi4_sclk⁽¹⁾
SPI4 Clock
IO
N7/ G1/ AA3/ V7/
AC8
spi4_d1
SPI4 Data. Can be configured as either MISO or MOSI.
IO
R4/ G6/ AB9/ U7/
AD6
spi4_d0
SPI4 Data. Can be configured as either MISO or MOSI.
IO
N9/ F2/ AB3/ V6/
AB8
spi4_cs0
SPI4 Chip Select
IO
P9/ F3/ AA4/ U6/
AB5
spi4_cs1
SPI4 Chip Select
IO
P4 / Y1
spi4_cs2
SPI4 Chip Select
IO
R3 / W9
spi4_cs3
SPI4 Chip Select
IO
T2 / V9
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between V_IH and V_IL must be less than V_HYS.
4.4.11 Quad Serial Peripheral Interface (QSPI)
NOTE
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Memory Booting / SPI/QSPI Flash Devices section of the device TRM.
SIGNAL NAME
qspi1_sclk
qspi1_rtclk
qspi1_d0
qspi1_d1
qspi1_d2
Table 4-14. QSPI Signal Descriptions
DESCRIPTION
QSPI1 Serial Clock
QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
QSPI1 Data[1]. Input read data in all modes.
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
TYPE
IO
I
IO
IO
IO
BALL
R2
R3
U1
P3
U2
98
Terminal Configuration and Functions
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