TDA2EG Datasheet, PDF (174/393 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 23mm Package (ABC Package) Silicon Revision 2.0

TDA2EG
SPRS958B – MARCH 2016 – REVISED JANUARY 2017
xi_osc1
Device
xo_osc1
vssa_osc1
www.ti.com
NC
SPRS906_CLK_07
Figure 6-8. 1.8-V LVCMOS-Compatible Clock Input
Table 6-7 summarizes the OSC1 input clock electrical characteristics.
Table 6-7. OSC1 Input Clock Electrical Characteristics—Bypass Mode
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
f
Frequency
Range from 12 to 38.4
MHz
C_IN
Input capacitance
I_IN
Input current (3.3V mode)
t_sX
Start-up time⁽¹⁾
2.819
4
3.019
6
See⁽²⁾
3.219
pF
10
µA
ms
(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 6-6, t_sX parameter.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in
application mode and receives a wave. The switching time in this case is about 100 μs.
Table 6-8 details the OSC1 input clock timing requirements.
Table 6-8. OSC1 Input Clock Timing Requirements
NAME
CK0
CK1
1/
t_c(xiosc1)
DESCRIPTION
Frequency, xi_osc1
t_w(xiosc1) Pulse duration, xi_osc1 low or high
t_j(xiosc1) Period jitter⁽¹⁾, xi_osc1
MIN
TYP
MAX
Range from 12 to 38.4
0.45 *
t_c(xiosc1)
0.55 *
t_c(xiosc1)
0.01 ×
t_c(xiosc1)
(3)
t_R(xiosc1) Rise time, xi_osc1
t_F(xiosc1) Fall time, xi_osc1
Ethernet and MLB not used
t_j(xiosc1) Frequency accuracy⁽²⁾, xi_osc1
Ethernet RGMII and RMII
using derived clock
Ethernet MII using derived
clock
MLB using derived clock
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02*tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
5
5
±200
±50
±100
±50
UNIT
MHz
ns
ns
ns
ns
ppm
174 Clock Specifications
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