TDA2EG Datasheet, PDF (152/393 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 23mm Package (ABC Package) Silicon Revision 2.0

TDA2EG
SPRS958B – MARCH 2016 – REVISED JANUARY 2017
www.ti.com
(1) V_ITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. V_ITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, V_HYST. V_HYST is the difference
between the V_ITH threshold and the V_ITL threshold.
(4) V_ITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mV_PP beyond 450 MHz.
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and
variations below 450 MHz.
(7) This number corresponds to the VOD_MAX transmitter.
(8) Common mode is defined as the average voltage level of X and Y: V_CMRX = (V_X + V_Y) / 2.
(9) Common mode ripple may be due to t_R or t_F and transmission line impairments in the PCB.
(10) For more information regarding the pin name (or ball name) and corresponding signal name, see Table 4-7 ,CSI 2 Signal Descriptions.
5.7.7 BC1833IHHV Buffers DC Electrical Characteristics
Table 5-15 summarizes the DC electrical characteristics for BC1833IHHV Buffers.
Table 5-15. BC1833IHHV Buffers DC Electrical Characteristics
PARAMETER
Signal Names in MUXMODE 0: on_off;
Balls: Y11;
1.8-V Mode
V_OH
Output high-level threshold (I_OH = 2 mA)
V_OL
I_DRIVE
I_IN
I_OZ
C_PAD
3.3-V Mode
V_OH
V_OL
I_DRIVE
I_IN
I_OZ
C_PAD
Output low-level threshold (I_OL = 2 mA)
Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V
Input current at each I/O pin
I_OZ(I_PAD Current) for BIDI cell. This current is contributed by
the tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and
the Max(I_(PAD)) is measured and is reported as I_OZ
Pad capacitance (including package capacitance)
Output high-level threshold (I_OH = 100 µA)
Output low-level threshold (I_OL = 100 µA)
Pin Drive strength at PAD Voltage = 0.45V or VDDS-0.45V
Input current at each I/O pin
I_OZ(I_PAD Current) for BIDI cell. This current is contributed by
the tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and
the Max(I_(PAD)) is measured and is reported as I_OZ
Pad capacitance (including package capacitance)
MIN
VDDS-
0.45
6
6
VDDS-0.2
6
NOM
5.7.8 USBPHY DC Electrical Characteristics
MAX UNIT
V
0.45
V
mA
12
µA
6
µA
4
pF
V
0.2
V
mA
60
µA
60
µA
4
pF
NOTE
USB1 instance is compliant with the USB3.0 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the USB3.0 Specification Rev 1.0 dated Jun 6,
2011.
152 Specifications
Submit Documentation Feedback
Product Folder Links: TDA2EG
Copyright © 2016–2017, Texas Instruments Incorporated