TDA2EG Datasheet, PDF (1/393 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 23mm Package (ABC Package) Silicon Revision 2.0

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TDA2EG
SPRS958B – MARCH 2016 – REVISED JANUARY 2017
TDA2Ex SoC for Advanced Driver Assistance Systems (ADAS)
23mm Package (ABC Package)
Silicon Revision 2.0
1 Device Overview
1.1 Features
1
• Architecture Designed for ADAS Applications
• Video, Image, and Graphics Processing Support
– Full-HD Video (1920 × 1080p, 60 fps)
– Multiple Video Input and Video Output
• ARM® Cortex®-A15 Microprocessor Subsystem
• C66x Floating-Point VLIW DSP
– Fully Object-Code Compatible With C67x and
C64x+
– Up to Thirty-two 16 × 16-Bit Fixed-Point
Multiplies per Cycle
• Up to 512KB of On-Chip L3 RAM
• Level 3 (L3) and Level 4 (L4) Interconnects
• DDR3/DDR3L Memory Interface (EMIF) Module
– Supports up to DDR3-1333 (667 MHz)
– Up to 2GB Across Single Chip Select
• Dual ARM® Cortex®-M4 Image Processing Units
(IPU)
• IVA-HD Subsystem
• Display Subsystem
– Display Controller With DMA Engine and up to
Three Pipelines
– HDMI™ Encoder: HDMI 1.4a and DVI 1.0
Compliant
• Single-Core PowerVR® SGX544 3D GPU
• 2D-Graphics Accelerator (BB2D) Subsystem
– Vivante™ GC320 Core
• Video Processing Engine (VPE)
• One Video Input Port (VIP) Module
– Support for up to Four Multiplexed Input Ports
• General-Purpose Memory Controller (GPMC)
• Enhanced Direct Memory Access (EDMA)
Controller
• 2-Port Gigabit Ethernet (GMAC)
– Up to Two External Ports, One Internal
• Sixteen 32-Bit General-Purpose Timers
• 32-Bit MPU Watchdog Timer
• Six High-Speed Inter-Integrated Circuit (I²C) Ports
• Ten Configurable UART/IrDA/CIR Modules
• Four Multichannel Serial Peripheral Interfaces
(McSPI)
• Quad SPI Interface (QSPI)
• SATA Interface
• Eight Multichannel Audio Serial Port (McASP)
Modules
• SuperSpeed USB 3.0 Dual-Role Device
• High-Speed USB 2.0 Dual-Role Device
• High-Speed USB 2.0 On-The-Go
• Four MultiMedia Card/Secure Digital/Secure Digital
Input Output Interfaces (MMC/SD/SDIO)
• PCI Express® 3.0 Port With Integrated PHY
– One 2-lane Gen2-Compliant Port
– or Two 1-lane Gen2-Compliant Ports
• Dual Controller Area Network (DCAN) Modules
– CAN 2.0B Protocol
• MIPI^® CSI-2 Camera Serial Interface
• Up to 215 General-Purpose I/O (GPIO) Pins
• Real-Time Clock Subsystem (RTCSS)
• Device Security Features
– Hardware Crypto Accelerators and DMA
– Firewalls
– JTAG Lock
– Secure Keys
– Secure ROM and Boot
• Power, Reset, and Clock Management
• On-Chip Debug With CTools Technology
• 28-nm CMOS Technology
• 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA
(ABC)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.