TDA2EG Datasheet, PDF (171/393 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 23mm Package (ABC Package) Silicon Revision 2.0

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xi_osc0
TDA2EG
SPRS958B – MARCH 2016 – REVISED JANUARY 2017
Device
xo_osc0
vssa_osc0
NC
SPRS906_CLK_04
Figure 6-4. 1.8-V LVCMOS-Compatible Clock Input
Table 6-3 summarizes the OSC0 input clock electrical characteristics.
Table 6-3. OSC0 Input Clock Electrical Characteristics—Bypass Mode
NAME
f
C_IN
I_IN
DESCRIPTION
Frequency
Input capacitance
Input current (3.3V mode)
MIN
2.184
4
TYP
19.2, 20, 27
2.384
6
MAX
2.584
10
Table 6-4 details the OSC0 input clock timing requirements.
UNIT
MHz
pF
µA
Table 6-4. OSC0 Input Clock Timing Requirements
NAME
CK0
1/
t_c(xiosc0)
Frequency, xi_osc0
DESCRIPTION
MIN
TYP
19.2, 20, 27
MAX
CK1
t_w(xiosc0) Pulse duration, xi_osc0 low or high
t_j(xiosc0) Period jitter⁽¹⁾, xi_osc0
t_R(xiosc0) Rise time, xi_osc0
t_F(xiosc0) Fall time, xi_osc0
t_j(xiosc0) Frequency accuracy⁽²⁾, xi_osc0
0.45 *
t_c(xiosc0)
Ethernet and MLB not used
Ethernet RGMII and RMII
using derived clock
Ethernet MII using derived
clock
MLB using derived clock
0.55 *
t_c(xiosc0)
0.01 ×
t_c(xiosc0)
5
5
±200
±50
±100
±50
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
UNIT
MHz
ns
ns
ns
ns
ppm
xi_osc0
CK0
CK1
Figure 6-5. xi_osc0 Input Clock
CK1
SPRS906_CLK_05
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Clock Specifications 171