SM320C6424-EP_14 Datasheet, PDF (98/237 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SM320C6424-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS580 – JUNE 2009
www.ti.com
The PINMUX1.PCIEN field is read-only, and its setting is determined by the PCIEN configuration pin.
Based on the PCIEN configuration pin setting, the 27 pins in the Host Block defaults to either PCI or GPIO
function.
In addition, the VDD3P3V_PWDN.HOST field determines the power state of the Host Block pins. The
Host Block pins default to powered up. For more details on the VDD3P3V_PWDN.HOST field, see
Section 3.2, Power Considerations.
3.7.3.4 PCI Data Block
This block of 3 pins consists of 3 PCI Address/Data pins—AD30, AD28, AD26. The PINMUX1.PCIEN
register field affects the pin functions in the PCI Data Block.
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the
following Pin Mux Blocks: Host Block, EMIFA Block Sub-Block 0 and Sub-Block 3, PCI Data Block, and
GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.
The 3 pins in the PCI Data Block are not muxed with any other peripherals. However, the
PINMUX1.PCIEN field controls the internal pullup/pulldown resistors on these pins. For PCI operation
(PCIEN = 1), the internal pullup/pulldown resistors are disabled. If the device does not support PCI
(PCIEN = 0), the internal pullup/pulldown resistors on these pins are enabled so that the user can leave
these pins unconnected on the board.
Table 3-22 shows the Host Block pin selection based on PINMUX1.PCIEN setting.
PINMUX1.PCIEN
0
1
Table 3-22. PCI Data Block Pin Control
BLOCK FUNCTION
No Connect Pins
(Default if PCIEN = 0)
PCI
(Default if PCIEN = 1)
RESULTING PIN FUNCTIONS
No Connect Pins
Internal pullup/pulldown enabled. Leave these three pins unconnected on the board.
PCI: AD26, AD28, AD30
3.7.3.5 GPIO Block Muxing
This block of 4 pins consists of PCI and GPIO muxed pins. The PINMUX1.PCIEN register field selects the
pin functions in the GPIO Block.
Table 3-23 summarizes the 4 pins in the GPIO Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
Table 3-23. GPIO Block Muxed Pins Selection
SIGNAL
MULTIPLEXED FUNCTIONS
PCI
GPIO
NAME
FUNCTION
SELECT
FUNCTION
SELECT
AD0/GP[0]
AD0
GP[0]
AD1/GP[1]
AD2/GP[2]
AD1
AD2
PCIEN = 1⁽¹⁾
GP[1]
GP[2]
PCIEN = 0⁽¹⁾
AD4/GP[3]
AD4
GP[3]
(1) If PCIEN = 1, the internal pullup/pulldown on all GPIO Block pins are disabled. If PCIEN = 0, the internal pullup/pulldown on all GPIO
Block pins are enabled.
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, PCI pins span across the
following Pin Mux Blocks: Host Block, EMIFA Block Sub-Block 0 and Sub-Block 3, PCI Data Block, and
GPIO Block. For proper PCI operation, PCI must be selected in all of these Pin Mux Blocks.
Table 3-24 provides a different view of the GPIO Block pin muxing, showing the GPIO Block function
based on PINMUX1.PCIEN setting. The selection options are also shown pictorially in Figure 3-10.
98
Device Configurations
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