SM320C6424-EP_14 Datasheet, PDF (68/237 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

SM320C6424-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS580 – JUNE 2009
www.ti.com
Table 3-5. User-Select Multiplier Fastboot Modes (FASTBOOT = 1)
DEVICE BOOT AND
CONFIGURATION PINS
BOOTMODE[3:0] PCIEN
0000
0001
0010
0011
0100
0 or 1
0
1
0
1
0 or 1
0 or 1
0101
0 or 1
0110
0111
0 or 1
0 or 1
1000
0 or 1
1001
1010
1011
1100
1101
1110
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
1111
0 or 1
BOOT DESCRIPTION⁽¹⁾
C6424 DMP
(Master/Slave)
No Boot (Emulation Boot)
Reserved
PCI Boot without Auto
Initialization
HPI Boot
PCI Boot with Auto
Initialization
Reserved
EMIFA ROM FASTBOOT
with AIS
I2C Boot
[FAST MODE]⁽³⁾
16-bit SPI Boot
[McBSP0]
NAND Flash Boot
UART Boot without
Hardware Flow Control
[UART0]
EMIFA ROM FASTBOOT
without AIS
VLYNQ Boot
Reserved
Reserved
Reserved
UART Boot with
Hardware Flow Control
[UART0]
24-bit SPI Boot
(McBSP0 + GP[97])
Master
–
Slave
Slave
Slave
–
Master
Master
Master
Master
Master
Master
Slave
–
–
–
Master
Master
PLLC1 CLOCK SETTING AT BOOT
PLL
CLKDIV1 DOMAIN
MODE⁽²⁾ (SYSCLK1 DIVIDER)
Bypass
/1
–
–
DEVICE
FREQUENCY
(SYSCLK1)
CLKIN
–
Table 3-6
/2
Table 3-6
Table 3-6
/2
Table 3-6
Table 3-6
/2
Table 3-6
–
–
–
Table 3-6
/2
Table 3-6
Table 3-6
/2
Table 3-6
Table 3-6
/2
Table 3-6
/2
Table 3-6
Table 3-6
Table 3-6
/2
Table 3-6
Table 3-6
/2
x20
/2
–
–
–
–
–
–
Table 3-6
/2
Table 3-6
CLKIN x20 / 2
–
–
–
Table 3-6
x20
/2
CLKIN x20 / 2
DSPBOOTADDR
(DEFAULT) ⁽¹⁾
0x0010 0000
–
0x0010 0000
0x0010 0000
0x0010 0000
–
0x0010 0000
0x0010 0000
0x0010 0000
0x0010 0000
0x0010 0000
–
0x0010 0000
–
–
–
0x0010 0000
0x0010 0000
(1) For all boot modes that default to DSPBOOTADDR = 0x0010 0000, the bootloader code disables all C64x+ cache (L2, L1P, and L1D)
so that upon exit from the bootloader code, all C64x+ memories are configured as all RAM. If cache use is required, the application
code must explicitly enable the cache.For more information on the bootloader, see the Using the TMS320C642x Bootloader Application
Report (literature number SPRAAK5).
(2) Any supported PLL MODE is available. [See Table 3-6 for supported C6424 PLL MODE options].
(3) I2C Boot (BOOTMODE[3:0] = 0101b) is only available if the MXI/CLKIN frequency is between 21 MHz to 30 MHz. I2C Boot is not
available for MXI/CLKIN frequencies less than 21 MHz.
Table 3-6. PLL Multiplier Selection (PLLMS[2:0]) in User-Select Multiplier Fastboot Modes
(FASTBOOT = 1)
DEVICE BOOT AND
CONFIGURATION PINS
PLLMS[2:0]
000
001
010
011
100
101
110
111
PLL MODE
x20
x15
x16
x18
x22
x25
x27
x30
PLLC1 CLOCK SETTING AT BOOT
CLKDIV1 DOMAIN
(SYSCLK1 DIVIDER)
/2
/2
/2
/2
/2
/2
/2
/2
DEVICE FREQUENCY (SYSCLK1)
CLKIN x20 / 2
CLKIN x15 / 2
CLKIN x16 / 2
CLKIN x18 / 2
CLKIN x22 / 2
CLKIN x25 / 2
CLKIN x27 / 2
CLKIN x30 / 2
68
Device Configurations
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