SM320C6424-EP_14 Datasheet, PDF (1/237 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

www.ti.com
1 Introduction
1.1 Features
• High-Performance Digital Signal Processor
(C6424)
– 2.5-, 2-, 1.67-, 1.43-ns Instruction Cycle
Time
– 400-, 500-, 600-, 700-MHz C64x+™ Clock
Rate
– Eight 32-Bit C64x+ Instructions/Cycle
– 3200, 4000, 4800, 5600 MIPS
– Fully Software-Compatible With C64x
– Commercial and Automotive (Q or S suffix)
Grades
– Low-Power Device (L suffix)
• VelociTI.2™ Extensions to VelociTI™
Advanced Very-Long-Instruction-Word (VLIW)
SM320C64x+™ DSP Core
– Eight Highly Independent Functional Units
With VelociTI.2 Extensions:
• Six ALUs (32-/40-Bit), Each Supports
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned
Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements
• Protected Mode Operation
• Exceptions Support for Error Detection
and Program Redirection
• Hardware Support for Modulo Loop
Auto-Focus Module Operation
• C64x+ Instruction Set Features
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– VelociTI.2 Increased Orthogonality
– C64x+ Extensions
• Compact 16-bit Instructions
• Additional Instructions to Support
Complex Multiplies
SM320C6424-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS580 – JUNE 2009
• C64x+ L1/L2 Memory Architecture
– 256K-Bit (32K-Byte) L1P Program
RAM/Cache [Flexible Allocation]
– 640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation]
– 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
• Endianess: Supports Both Little Endian and
Big Endian
• External Memory Interfaces (EMIFs)
– 32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)
• Supports up to 333-MHz (data rate) bus
and interfaces to DDR2-400 SDRAM
– Asynchronous 16-Bit Wide EMIF (EMIFA)
With up to 128M-Byte Address Reach
• Flash Memory Interfaces
– NOR (8-/16-Bit-Wide Data)
– NAND (8-/16-Bit-Wide Data)
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
• Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Two UARTs (One with RTS and CTS Flow
Control)
• Master/Slave Inter-Integrated Circuit (I²C
Bus™)
• Two Multichannel Buffered Serial Ports
(McBSPs)
– I2S and TDM
– AC97 Audio Codec Interface
– SPI
– Standard Voice Codec Interface (AIC12)
– Telecom Interfaces – ST-Bus, H-100
– 128 Channel Mode
• Multichannel Audio Serial Port (McASP0)
– Four Serializers and SPDIF (DIT) Mode
• 16-Bit Host-Port Interface (HPI)
• 32-Bit 33-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated