SM320C6424-EP_14 Datasheet, PDF (227/237 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

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6.21.1 GPIO Peripheral Register Description(s)
SM320C6424-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS580 – JUNE 2009
HEX ADDRESS RANGE
0x01C6 7000
0x01C6 7004
0x01C6 7008
0x01C6 700C
0x01C6 7010
0x01C6 7014
0x01C6 7018
0x01C6 701C
0x01C6 7020
0x01C6 7024
0x01C6 7028
0x01C6 702C
0x01C6 7030
0x01C6 7034
0x01C6 7038
0x01C6 703C
0x01C6 7040
0x01C6 7044
0x01C6 7048
0x01C6 704C
0x01C6 7050
0x01C6 7054
0x01C6 7058
0x01C6 705C
0x01C6 7060
0x01C6 7064
0x01C6 7068
0x01C6 706C
0x01C6 7070
0x01C6 7074
0x01C6 7078
0x01C6 707C
0x01C6 7080
0x01C6 7084
0x01C6 7088
0x01C6 708C
0x01C6 7090
0x01C6 7094
0x01C6 7098
0x01C6 709C
0x01C6 70A0
Table 6-88. GPIO Registers
ACRONYM
REGISTER NAME
PID
Peripheral Identification Register
-
Reserved
BINTEN
GPIO interrupt per-bank enable
GPIO Banks 0 and 1
-
Reserved
DIR01
GPIO Banks 0 and 1 Direction Register (GP[0:31])
OUT_DATA01 GPIO Banks 0 and 1 Output Data Register (GP[0:31])
SET_DATA01 GPIO Banks 0 and 1 Set Data Register (GP[0:31])
CLR_DATA01 GPIO Banks 0 and 1 Clear data for banks 0 and 1 (GP[0:31])
IN_DATA01
GPIO Banks 0 and 1 Input Data Register (GP[0:31])
SET_RIS_TRIG01 GPIO Banks 0 and 1 Set Rising Edge Interrupt Register (GP[0:31])
CLR_RIS_TRIG01 GPIO Banks 0 and 1 Clear Rising Edge Interrupt Register (GP[0:31])
SET_FAL_TRIG01 GPIO Banks 0 and 1 Set Falling Edge Interrupt Register (GP[0:31])
CLR_FAL_TRIG01 GPIO Banks 0 and 1 Clear Falling Edge Interrupt Register (GP[0:31])
INSTAT01
GPIO Banks 0 and 1 Interrupt Status Register (GP[0:31])
GPIO Banks 2 and 3
DIR23
GPIO Banks 2 and 3 Direction Register (GP[32:63])
OUT_DATA23 GPIO Banks 2 and 3 Output Data Register (GP[32:63])
SET_DATA23 GPIO Banks 2 and 3 Set Data Register (GP[32:63])
CLR_DATA23 GPIO Banks 2 and 3 Clear Data Register (GP[32:63])
IN_DATA23
GPIO Banks 2 and 3 Input Data Register (GP[32:63])
SET_RIS_TRIG23 GPIO Banks 2 and 3 Set Rising Edge Interrupt Register (GP[32:63])
CLR_RIS_TRIG23 GPIO Banks 2 and 3 Clear Rising Edge Interrupt Register (GP[32:63])
SET_FAL_TRIG23 GPIO Banks 2 and 3 Set Falling Edge Interrupt Register (GP[32:63])
CLR_FAL_TRIG23 GPIO Banks 2 and 3 Clear Falling Edge Interrupt Register (GP[32:63])
INSTAT23
GPIO Banks 2 and 3 Interrupt Status Register (GP[32:63])
GPIO Bank 4 and 5
DIR45
GPIO Bank 4 and 5 Direction Register (GP[64:95])
OUT_DATA45 GPIO Bank 4 and 5 Output Data Register (GP[64:95])
SET_DATA45 GPIO Bank 4 and 5 Set Data Register (GP[64:95])
CLR_DATA45 GPIO Bank 4 and 5 Clear Data Register (GP[64:95])
IN_DATA45
GPIO Bank 4 and 5 Input Data Register (GP[64:95])
SET_RIS_TRIG45 GPIO Bank 4 and 5 Set Rising Edge Interrupt Register (GP[64:95])
CLR_RIS_TRIG45 GPIO Bank 4 and 5 Clear Rising Edge Interrupt Register (GP[64:95])
SET_FAL_TRIG45 GPIO Bank 4 and 5 Set Falling Edge Interrupt Register (GP[64:95])
CLR_FAL_TRIG45 GPIO Bank 4 and 5 Clear Falling Edge Interrupt Register (GP[64:95])
INSTAT45
GPIO Bank 4 and 5 Interrupt Status Register (GP[64:95])
GPIO Bank 6
DIR6
GPIO Bank 6 Direction Register (GP[96:110])
OUT_DATA6 GPIO Bank 6 Output Data Register (GP[96:110])
SET_DATA6 GPIO Bank 6 Set Data Register (GP[96:110])
CLR_DATA6 GPIO Bank 6 Clear Data Register (GP[96:110])
IN_DATA6
GPIO Bank 6 Input Data Register (GP[96:110])
SET_RIS_TRIG6 GPIO Bank 6 Set Rising Edge Interrupt Register (GP[96:110])
CLR_RIS_TRIG6 GPIO Bank 6 Clear Rising Edge Interrupt Register (GP[96:110])
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