SM320C6424-EP_14 Datasheet, PDF (39/237 Pages) Texas Instruments – FIXED-POINT DIGITAL SIGNAL PROCESSOR

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SM320C6424-EP
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS580 – JUNE 2009
Table 2-15. Peripheral Component Interconnect (PCI) Terminal Functions
SIGNAL
NAME
GDU ^TYPE(1)
NO.
OTHER ^{(2) (3)}
DESCRIPTION
PCI
EM_A[16]/PGNT/
GP[48]
EM_A[18]/PRST/
GP[46]
EM_A[19]/PREQ/
GP[45]
EM_A[20]/PINTA/
GP[44]
EM_A[12]/PCBE3/
GP[89]
HD3/VLYNQ_RXD2/
PCBE2 /GP[61]
HD11/MTXD3/
PCBE1/GP[69]
HRDY/MRXD2/
PCBE0/GP[80]
EM_A[9]/PIDSEL/
GP[92]
VLYNQ_CLOCK/
PCICLK/GP[57]
HD4/VLYNQ_RXD3/
PFRAME/GP[62]
HD5/VLYNQ_TXD0/
PIRDY/GP[63]
HD6/VLYNQ_TXD1/
PTRDY/GP[64]
HD7/VLYNQ_TXD2/
PDEVSEL/GP[65]
HD8/VLYNQ_TXD3/
PPERR/GP[66]
HD9/MCOL/
PSTOP/GP[67]
HD10/MCRS/
PSERR/GP[68]
HD12/MTXD2/
PPAR/GP[70]
B13 I/O/Z
A14 I/O/Z
C14 I/O/Z
C15 I/O/Z
B12 I/O/Z
B8 I/O/Z
A5 I/O/Z
C3 I/O/Z
C11 I/O/Z
A8 I/O/Z
C8 I/O/Z
A7 I/O/Z
C7 I/O/Z
B7 I/O/Z
A6 I/O/Z
C6 I/O/Z
B6 I/O/Z
C5 I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPU
DV_DD33
IPD
DV_DD33
IPU
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between the EMIFA, PCI, and GPIO.
In PCI mode, this pin is PCI bus grant (I)
THIS pin is multiplexed between the EMIFA, PCI, and GPIO.
In PCI mode, this pin is PCI reset (I)
This pin is multiplexed between the EMIFA, PCI, and GPIO.
In PCI mode, this pin is the PCI bus request (O/Z)
This pin is multiplexed between the EMIFA, PCI, and GPIO.
In PCI mode, this pin is the PCI interrupt A (O/Z)
This pin is multiplexed between EMIFA, PCI, and GPIO.
In PCI mode, this pin is the PCI command/byte enable 3 (I/O/Z).
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI command/byte enable 2 (I/O/Z)
This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO.
In PCI mode, this pin is the PCI command/byte enable 1 (I/O/Z)
This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO.
In PCI mode, this pin is the PCI command/byte enable 0 (I/O/Z)
This pin is multiplexed between EMIFA, PCI, and GPIO.
In PCI mode, this pin is the PCI initialization device select (I)
This pin is multiplexed between VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI clock (I)
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI frame (I/O/Z)
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI initiator ready (I/O/Z)
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI target ready (I/O/Z)
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI device select (I/O/Z)
This pin is multiplexed between HPI, VLYNQ, PCI, and GPIO.
In PCI mode, this pin is the PCI parity error (I/O/Z)
This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO.
In PCI mode, this pin is the PCI stop (I/O/Z)
This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO.
In PCI mode, this pin is the PCI system error (I/O/Z)
This pin is multiplexed between HPI, EMAC (MII), PCI, and GPIO.
In PCI mode, this pin is the PCI parity (I/O/Z)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. For more detailed information on pullup/pulldown resistors and situations where external
pullup/pulldown resistors are required, see Section 3.9.1, Pullup/Pulldown Resistors.
(3) Specifies the operating I/O supply voltage for each signal
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