RM48L930 Datasheet, PDF (97/147 Pages) Texas Instruments – RM48Lx30 16/32-Bit RISC Flash Microcontroller

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RM48L930
RM48L730
RM48L530
SPNS176 – SEPTEMBER 2011
4.19 Reset / Abort / Error Sources
Table 4-36. Reset/Abort/Error Sources
ERROR SOURCE
SYSTEM MODE
Precise write error (NCNB/Strongly Ordered)
Precise read error (NCB/Device or Normal)
Imprecise write error (NCB/Device or Normal)
CPU TRANSACTIONS
User/Privilege
User/Privilege
User/Privilege
Illegal instruction
User/Privilege
MPU access violation
B0 TCM (even) ECC single error (correctable)
User/Privilege
SRAM
User/Privilege
B0 TCM (even) ECC double error (non-correctable)
User/Privilege
B0 TCM (even) uncorrectable error (i.e. redundant address
decode)
B0 TCM (even) address bus parity error
B1 TCM (odd) ECC single error (correctable)
User/Privilege
User/Privilege
User/Privilege
B1 TCM (odd) ECC double error (non-correctable)
User/Privilege
B1 TCM (odd) uncorrectable error (i.e. redundant address
decode)
User/Privilege
B1 TCM (odd) address bus parity error
User/Privilege
FLASH
FMC correctable error - Bus1 and Bus2 interfaces
User/Privilege
FMC uncorrectable error - Bus1 accesses
(does not include address parity error)
User/Privilege
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank
accesses)
User/Privilege
FMC uncorrectable error - address parity error on Bus1
accesses
User/Privilege
FMC correctable error - Accesses to EEPROM bank
User/Privilege
FMC uncorrectable error - Accesses to EEPROM bank
User/Privilege
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
External imprecise error on write (Illegal transaction with ok
response)
User/Privilege
Memory access permission violation
User/Privilege
Memory parity error
User/Privilege
DMM TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
response)
User/Privilege
External imprecise error on write (Illegal transaction with ok
response)
User/Privilege
HET TU (HTU)
NCNB (Strongly Ordered) transaction with slave error response User/Privilege
External imprecise error (Illegal transaction with ok response)
User/Privilege
Memory access permission violation
User/Privilege
ERROR RESPONSE
Precise Abort (CPU)
Precise Abort (CPU)
Imprecise Abort (CPU)
Undefined Instruction Trap
(CPU) ⁽¹⁾
Abort (CPU)
ESM
Abort (CPU), ESM =>
nERROR
ESM => NMI
ESM => NMI
ESM
Abort (CPU), ESM =>
nERROR
ESM => NMI
ESM => NMI
ESM
Abort (CPU), ESM =>
nERROR
ESM => nERROR
ESM => NMI
ESM
ESM
ESM
ESM
ESM
ESM
ESM
ESM
Interrupt => VIM
Interrupt => VIM
ESM
ESM HOOKUP
group.channel
n/a
n/a
n/a
n/a
n/a
1.26
3.3
2.6
2.10
1.28
3.5
2.8
2.12
1.6
3.7
3.7
2.4
1.35
1.36
1.5
1.13
1.2
1.3
1.5
1.13
n/a
n/a
1.9
(1) The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
Copyright © 2011, Texas Instruments Incorporated
System Information and Electrical Specifications
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