RM48L930 Datasheet, PDF (82/147 Pages) Texas Instruments – RM48Lx30 16/32-Bit RISC Flash Microcontroller

RM48L930
RM48L730
RM48L530
SPNS176 – SEPTEMBER 2011
4.14.2.4 Write Timing (Synchronous RAM)
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EMIF_CLK
EMIF_CS[0]
EMIF_DQM[1:0]
EMIF_BA[1:0]
EMIF_ADDR[21:0]
EMIF_DATA[15:0]
EMIF_nRAS
EMIF_nCAS
EMIF_nWE
BASIC SDRAM
WRITE OPERATION
1
22
3
4
5
6
7
8
7
8
9
10
11
12
13
15
16
Figure 4-16. Basic SDRAM Write Operation
4.14.2.5 EMIF Asynchronous Memory Timing
Table 4-27. EMIF Asynchronous Memory Timing Requirements
NO.
Value
Unit
MIN
NOM
MAX
Reads and Writes
2
t_{w(EM_WAIT)}
Pulse duration, EMIFnWAIT
2E
ns
assertion and deassertion
Reads
12 t_{su(EMDV-EMOEH)}
Setup time, EMIFDATA[15:0]
3
ns
valid before EMIFnOE high
13 t_{h(EMOEH-EMDIV)}
Hold time, EMIFDATA[15:0]
0.5
ns
valid after EMIFnOE high
14 t_{su(EMOEL-EMWAIT)}
Setup Time, EMIFnWAIT
4E+3
ns
asserted before end of Strobe
Phase ⁽¹⁾
Writes
28 t_{su(EMWEL-EMWAIT)}
Setup Time, EMIFnWAIT
4E+3
ns
asserted before end of Strobe
Phase ⁽¹⁾
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMIFnWAIT must be asserted to add extended
wait states. Figure Figure 4-12 and Figure Figure 4-14 describe EMIF transactions that include extended wait states inserted during the
STROBE phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start
of where the HOLD phase would begin if there were no extended wait cycles.
82
System Information and Electrical Specifications
Copyright © 2011, Texas Instruments Incorporated
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