ADS52J90 Datasheet, PDF (95/149 Pages) Texas Instruments – Multichannel, Low-Power, High-Speed ADC

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12.1.1.3 Register 2h (address = 2h)
ADS52J90
SBAS690B – MAY 2015 – REVISED AUGUST 2015
Figure 94. Register 2h
15
14
13
PAT_MODES_FCLK[2:0]
R/W-0h
12
LOW_
LATENCY_EN
R/W-0h
11
AVG_EN
R/W-0h
10
SEL_PRBS_
PAT_FCLK
R/W-0h
9
8
PAT_MODES[2:0]
R/W-0h
7
6
5
4
3
2
1
0
PAT_
MODES[2:0]
SEL_PRBS_
PAT_GBL
OFFSET_CORR_DELAY_FROM_TX_TRIG[5:0]
R/W-0h
R/W-0h
R/W-0h
LEGEND: R/W = Read/Write; -n = value after reset
Table 51. Register 2h Field Descriptions
Bit
15-13
Field
PAT_MODES_FCLK[2:0]
12
LOW_LATENCY_EN
11
AVG_EN
10
SEL_PRBS_PAT_FCLK
9-7 PAT_MODES[2:0]
6
SEL_PRBS_PAT_GBL
Type
R/W
Reset
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
R/W
0h
5-0 OFFSET_CORR_DELAY_FROM_ R/W
0h
TX_TRIG[5:0]
Description
These bits enable different test patterns on the frame clock line;
see Table 52 for bit descriptions and the LVDS Test Pattern
Mode section for further details.
0 = Default latency with digital features supported
1 = Low-latency with digital features bypassed
0 = No digital averaging
1 = Enables digital averaging of two channels to improve signal-
to-noise ratio (SNR)
0 = Normal operation
1 = Enables the PRBS pattern to be generated on FCLK; see
the LVDS Test Pattern Mode section for further details.
These bits enable different test patterns on the LVDS data lines;
see Table 52 for bit descriptions and the LVDS Test Pattern
Mode section for further details.
0 = Normal operation
1 = Enables the PRBS pattern to be generated on all the LVDS
data lines; see the LVDS Test Pattern Mode section for further
details.
This is a part of an 8-bit control that initiates offset correction
after the TX_TRIG input pulse (each step is equivalent to one
sample delay); the remaining two MSB bits are the
OFFSET_CORR_DELAY_FROM_TX_TRIG[7:6] bits (bits 10-9)
in register 3.
Table 52. Pattern Mode Bit Description⁽¹⁾
PAT_MODES[2:0] or PAT_MODES_FCLK[2:0] or PAT_LVDSx[2:0]
000
001
010
011
100
101
110
111
DESCRIPTION
Normal operation
Sync
Deskew
Custom ⁽²⁾
All 1s
Toggle mode
All 0s
Ramp ⁽²⁾
(1) For detailed description, see Table 33.
(2) Either the custom or ramp pattern setting is required for PRBS pattern selection.
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