ADS52J90 Datasheet, PDF (45/149 Pages) Texas Instruments – Multichannel, Low-Power, High-Speed ADC

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ADS52J90
SBAS690B – MAY 2015 – REVISED AUGUST 2015
AIN1
AIN2
System Clock, f_S
t₁
t₂
t_AP
t_AP
Conversion Clock, f_C
Frame Clock Output, f_F
ADC1 Conversion
SERIAL_OUT1
N_LAT
ADC1o
ADC1e
t_PROP
t_PROP
Serialized output of ... SERIAL_IN1
SERIAL_IN1
Corresponding to ...
AIN1(t₁)
AIN2(t₂)
ADC2 Conversion
ADC2o
ADC2e
Serialized output of ... SERIAL_IN2
SERIAL_IN2
SERIAL_OUT2
Corresponding to ...
AIN3(t₁)
AIN4(t₂)
Figure 68. ADC to Output Mapping in 32-Input, 1X Mode in LVDS Interface Mode
The mapping of the subsequent-numbered ADC signals to subsequent-numbered SERIAL_OUT signals follows
the same pattern as indicated previously.
The serialized stream in SERIAL_OUT is a serialized representation of SERIAL_IN, which is the input word
coming into the serializer. By default, serialization is done LSB-first. By setting the MSB_FIRST bit, serialization
can be set to MSB-first.
The alignment of the frame clock, bit clock, and the serialized output data is illustrated in Figure 1 for 16-input
mode where the serialization factor is set to 12 bit, serialization is LSB-first, and the data rate is set to 1X mode.
Another case is shown in Figure 69 for 16-input mode. Here, the serialization factor is set to 14 bit, serialization
is MSB-first, and the data rate is set to 2X mode.
SERIAL_IN1 (D[13:0])
SERIAL_IN2 (D[13:0])
Data (DOUT)
Bit Clock (DCLK)
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 _D4 D3 D2 D1 _D0
Frame Clock (FCLK)
Figure 69. LVDS Output Signals Timing Diagram in 16-Input Mode with
14-Bit Serialization, MSB-First, 2X Data Rate Mode
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