ADS52J90 Datasheet, PDF (86/149 Pages) Texas Instruments – Multichannel, Low-Power, High-Speed ADC

ADS52J90
SBAS690B – MAY 2015 – REVISED AUGUST 2015
www.ti.com
9.3 Do's and Don'ts
Driving the inputs (analog or digital) beyond the power-supply rails. For device reliability, an input must not
go more than 300 mV below the ground pins or 300 mV above the supply pins. Exceeding these limits, even on
a transient basis, can cause faulty or erratic operation and can impair device reliability.
Driving the device signal input with an excessively high level signal. The device offers consistent and fast
overload recovery for an overload of upto 6 dBFS. For very large overload signals (> 6 dB of the linear input
signal range), TI recommends back-to-back Schottky clamping diodes at the input to limit the amplitude of the
input signal.
Using a clock source with excessive jitter, an excessively long input clock signal trace, or having other
signals coupled to the ADC clock signal trace. These situations cause the sampling instant vary, causing an
excessive output noise and a reduction in SNR performance. For a system with multiple devices, the clock tree
scheme must be used to apply an ADC clock. Excessive clock delay mismatch between devices can also lead to
latency mismatch and functional failure at the system level.
LVDS routing length mismatch. The routing length of all LVDS lines routing to the FPGA must be matched to
avoid any timing-related issues. For systems with multiple devices, the LVDS serialized data clock (DCLKP,
DCLKM) and the frame clock (FCLKP, FCLKM) of each individual device must be used to deserialize the
corresponding LDVS serialized data (DOUTP, DOUTM).
Failure to provide adequate heat removal. Use the appropriate thermal parameter listed in the Thermal
Information table and an ambient, board, or case temperature in order to calculate device junction temperature. A
suitable heat removal technique must be used to keep the device junction temperature below the maximum limit
of 105°C.
10 Power-Supply Recommendations
The device requires three supplies in order to operate properly. These supplies are AVDD_1P8, DVDD_1P8, and
DVDD_1P2. All supplies must be driven with low-noise sources to be able to achieve the best performance from
the device. When determining the drive current needed to drive each of the supplies of the device, a margin of
50-100% over the typical current might be needed to account for the current consumption across different modes
of operation.
10.1 Power Sequencing and Initialization
Figure 90 shows the suggested power-up sequencing and reset timing for the device. Note that the DVDD_1P2
supply must rise before the AVDD_1P8 supply. If the AVDD_1P8 supply rises before the DVDD_1P2 supply, the
AVDD_1P8 supply current is several times higher than the normal operating current until the time the DVDD_1P2
supply reaches the 1.2-V level.
The device requires register described in Table 43 to be written as part of the initialization.
Table 43. Initialization Register Details
INITIALIZATION REGISTER ADDRESS
0Ah
16-BIT DATA WORD TO BE WRITTEN
3000h
The initialization sequence is described below:
1. Power-up the supplies as indicated,
2. Apply a hardware reset pulse,
3. Write the initialization register listed in Table 43 through the SPI interface,
4. Write other device settings through the SPI interface, and
5. After a wait time, the device is ready for high accuracy operation.
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