ADS52J90 Datasheet, PDF (32/149 Pages) Texas Instruments – Multichannel, Low-Power, High-Speed ADC

ADS52J90
SBAS690B – MAY 2015 – REVISED AUGUST 2015
Sampling Instants
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8-Channel Input Mode
t₁ t₂ t₃ t₄ t5 t₆ t7 t8
Analog input, AIN1
System Clock, f_S
(External Clock)
Sampling Clock for Input 1, f_SAMP
(Internal Signal)
ADCIN1
Input to Odd
Sampling Circuit
Input to Even
Sampling Circuit
ADC1 Conversion
AIN1
AIN1
ADC1o
AIN1(t₁)
AIN1
ADC1e
AIN1(t₃)
AIN1
ADC1o
AIN1(t₅)
ADC1e
AIN1(t₇)
ADCIN2
Input to Odd
Sampling Circuit
Input to Even
Sampling Circuit
ADC2 Conversion
AIN1
AIN1
ADC2o
AIN1(t₂)
AIN1
ADC2e
AIN1(t₄)
AIN1
ADC2o
AIN1(t₆)
ADC2e
AIN1(t₈)
ADC Conversion Clock, f_C
(Internal Signal)
Figure 59. Input Sampling and Conversion Scheme (8-Input Mode)
Mapping the inputs of the odd and even sampling circuits of subsequent-numbered ADCs to subsequent-
numbered sets of input pairs repeats in a similar manner.
The sampling rate (f_SAMP) can be defined as the rate at which the device converts each analog input presented to
it. The relationship between the sampling rate and the system clock frequency is listed in Table 2 for the three
input modes.
Table 2. Sampling Rate and Input Clock Frequency
ANALOG INPUT MODE (Number of Input Channels)
16
32
8
SAMPLING RATE (f_SAMP)
f_S
0.5 × f_S
f_S
In 16-input mode, each ADC converts one input at a sampling rate equal to the system clock. In 32-input mode,
one ADC alternately converts two sets of inputs, each at a sampling rate that is half the system clock. In the 8-
input mode, two ADCs convert the same input in interleaved manner.
In 16-input mode, a ping-pong operation exists between two sampling circuits of one ADC that are sampling the
same input. The mismatch between the two sampling circuit bandwidths can result in an interleaving spur at
(f_S / 2 ± f_IN), where f_S is the frequency of the system clock and f_IN is the frequency of the input signal.
In 8-input mode, additional interleaving across two adjacent ADCs is present in addition to the ping-pong
operation between the two sampling circuits of the same ADC. This increased mismatch can result in significant
interleaving spurs at (f_S / 2 ± f_IN) and (f_S / 4 ± f_IN). The offset mismatch between the four sets of sampling circuits
can result in a spur at f_S / 4.
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