ADS52J90 Datasheet, PDF (49/149 Pages) Texas Instruments – Multichannel, Low-Power, High-Speed ADC

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ADS52J90
SBAS690B – MAY 2015 – REVISED AUGUST 2015
IN1
IN2
Analog
Inputs
ADC_RES
12-, 14-Bits
SER_DATA_RATE
12-, 14-, 16-Bits
Test Pattern
Setting
EN_JESD DIS_LVDS
SER_DATA_RATE
MSB_
FIRST
1X, 2X
Mode
ADC1
ADCOUT1
12, 14
ADCOUT2
ADC2
DIGOUT1
16
DIGOUT2
Digital
Processing
(Bypassable)
DIGRES1
12, 14, 16
DIGRES2
SERIAL_
IN1
12, 14, 16
SERIAL_
IN2
LVDS_IN1
12, 14, 16
LVDS_IN16
Truncation
Test Pattern
Insertion
LVDS,
JESD
Selection
12, 14, 16
LVDS
Serializer
SERIAL_
OUT1
SERIAL_
OUT16
CML_IN1
1X, 2X
Mode
DOUT1
Output
Multiplexer
DOUT16
FCLK
DCLK
LVDS Outputs
CML1_OUT
IN16
ADCOUT16
ADC16
DIGOUT16
A/D Conversion and Digital Processing
Sampling Clock,
fSAMP
Conversion Clock, fC
DIGRES16
SERIAL_
IN16
Data Formatting
Frame Clock, fF
12, 14, 16
CML_IN16
12, 14, 16
JESD Tx Block
(Transport, Link, and Physical Layers)
CML Outputs
CML8_OUT
SYNC~,
SYSREF
SER_
DATA_
RATE
DATA_
PACKING
ADC_RES Version,
8, 4,
Subclass 2_LANE
Internal Clock Generation and
Clock Tree
System Clock, fS
Figure 72. JESD Interface Connection to the Digital Processing Output
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