ADS52J90 Datasheet, PDF (66/149 Pages) Texas Instruments – Multichannel, Low-Power, High-Speed ADC

ADS52J90
SBAS690B – MAY 2015 – REVISED AUGUST 2015
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The jitter cleaners CDCM7005, CDCE72010, or LMK048X series are suitable to generate the system clock and
enable high performance. Figure 83 shows a clock distribution network.
FPGA Clock,
Noisy Clock
n × (5 MHz to 100 MHz)
TI Jitter Cleaner
LMK048X
CDCE72010
CDCM7005
5-MHz to 100-MHz
ADC CLK
CDCLVP1208
LMK0030X
LMK01000
The CDCE72010 has 10
outputs
8 Synchronized
DUT System CLKs
Figure 83. System Clock Distribution Network
8.3.11 Analog Input and Driving Circuit
8.3.11.1 Signal Input
The analog input to the device can be either ac- or dc-coupled. In ac-coupling, the input common-mode required
for device functionality can be forced with the common-mode voltage, generated internally by the device (that
comes at the VCM pin) through a resistor, as shown in Figure 84. The resistor and capacitor values used for
coupling determines the high-pass filter corner of the input circuit; thus, these values are chosen with the
frequency of interest in mind.
Input 2-V_PP
Differential
10 nF
25 3
VCM
25 3
1 2F
50 3
6.8 pF
50 3
10 nF
INPx
Device
INMx
VCM
CM Buffer
Internal
Reference
66
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Figure 84. AC Coupling
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