TMS320C6652 Datasheet, PDF (91/236 Pages) Texas Instruments – TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.6.2.2 PLL Controller Divider Register (PLLDIV2, PLLDIV5, PLLDIV8)
The PLL Controller Divider Registers (PLLDIV2, PLLDIV5, and PLLDIV8) are shown in Figure 6-5 and
described in Table 6-11. The default values of the RATIO field on a reset for PLLDIV2, PLLDIV5, and
PLLDIV8 are different and mentioned in the footnote of Figure 6-5.
Figure 6-5. PLL Controller Divider Register (PLLDIVn)
31
16
15
Reserved
Dn⁽¹⁾ EN
R-0
R/W-1
Legend: R/W = Read/Write; R = Read only; -n = value after reset
(1) D2EN for PLLDIV2; D5EN for PLLDIV5; D8EN for PLLDIV8
(2) n=02h for PLLDIV2; n=04h for PLLDIV5; n=3Fh for PLLDIV8
14
Reserved
R-0
8
7
0
RATIO
R/W-n ⁽²⁾
BIT
31-16
15
FIELD
Reserved
DnEN
14-8
7-0
Reserved
RATIO
Table 6-11. PLL Controller Divider Register (PLLDIVn) Field Descriptions
DESCRIPTION
Reserved.
Divider Dn enable bit. (see footnote of Figure 6-5)
• 0 = Divider n is disabled.
• 1 = No clock output. Divider n is enabled.
Reserved. The reserved bit location is always read as 0. A value written to this field has no effect.
Divider ratio bits. (see footnote of Figure 6-5)
• 0h = ÷1. Divide frequency by 1.
• 1h = ÷2. Divide frequency by 2.
• 2h = ÷3. Divide frequency by 3.
• 3h = ÷4. Divide frequency by 4.
• 4h - 4Fh = ÷5 to ÷80. Divide frequency by 5 to divide frequency by 80.
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