TMS320C6652 Datasheet, PDF (201/236 Pages) Texas Instruments – TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
8.3.8 Reset Status Clear (RESET_STAT_CLR) Register
The RESET_STAT bits can be cleared by writing 1 to the corresponding bit in the RESET_STAT_CLR
register. The Reset Status Clear Register is shown in Figure 8-7 and described in Table 8-9.
Figure 8-7. Reset Status Clear Register (RESET_STAT_CLR)
31
30
GR
Reserved
RW, +0
R, + 000 0000 0000 0000 0000 0000
Legend: R = Read only; RW = Read/Write; -n = value after reset
2
1
Reserved
RW,+0
0
LR0
RW,+0
Table 8-9. Reset Status Clear Register (RESET_STAT_CLR) Field Descriptions
BIT FIELD
31
GR
30-2
1
0
Reserved
Reserved
LR0
DESCRIPTION
Global reset clear bit
• 0 = Writing 0 has no effect.
• 1 = Writing 1 to the GR bit clears the corresponding bit in the RESET_STAT register.
Reserved.
Reserved.
CorePac0 reset clear bit
• 0 = Writing 0 has no effect.
• 1 = Writing 1 to the LR0 bit clears the corresponding bit in the RESET_STAT register.
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Device Configuration 201