TMS320C6652 Datasheet, PDF (126/236 Pages) Texas Instruments – TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
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MPU0
MPU1
MPU2
MPU3
MPU4
Table 6-34. MPU Memory Regions
MEMORY PROTECTION
Main CFG TeraNet
QM_SS DATA PORT
QM_SS CFG PORT
Semaphore
EMIF16
START ADDRESS
0x01D00000
0x34000000
0x02A00000
0x02640000
0x70000000
END ADDRESS
0x026207FF
0x340BFFFF
0x02ABFFFF
0x026407FF
0x7FFFFFFF
Table 6-35 shows the privilege ID of each CORE and every mastering peripheral. Table 6-35 also shows
the privilege level (supervisor vs. user), and access type (instruction read vs. data/DMA read or write) of
each master on the device. In some cases, a particular setting depends on software being executed at the
time of the access or the configuration of the master peripheral.
PRIVILEGE ID MASTER
0
CorePac0
1
Reserved
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
uPP
7
EMAC
8
QM_PKTDMA
9
Reserved
10
QM_second
11
PCIe
12
DAP
13
Reserved
14
Reserved
15
Reserved
Table 6-35. Privilege ID Settings
PRIVILEGE LEVEL
SW dependant, driven by MSMC
User
User (C6654 Only)
User
User
Supervisor (C6654 Only)
Driven by Debug_SS
ACCESS
TYPE
DMA
DMA
DMA
DMA
DMA
DMA
DMA
126 Detailed Description
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