TMS320C6652 Datasheet, PDF (18/236 Pages) Texas Instruments – TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
SIGNAL NAME
LENDIAN †
BOOTMODE00 †
BOOTMODE01†
BOOTMODE02 †
BOOTMODE03 †
BOOTMODE04 †
BOOTMODE05 †
BOOTMODE06 †
BOOTMODE07 †
BOOTMODE08 †
BOOTMODE09 †
BOOTMODE10 †
BOOTMODE11 †
BOOTMODE12 †
PCIESSMODE0 †
PCIESSMODE1 †
PCIESSEN ‡
CORECLKP
CORECLKN
DDRCLKP
DDRCLKN
PCIECLKP
PCIECLKN
MCMCLKP
MCMCLKN
AVDDA1
AVDDA2
SYSCLKOUT
HOUT
NMI
LRESET
LRESETNMIEN
CORESEL0
CORESEL1
RESETFULL
RESET
POR
RESETSTAT
BOOTCOMPLETE
PTV15
Table 4-2. Terminal Functions — Signals and Control by Function
BALL
NO. TYPE IPD/IPU
T25 IOZ
R25 IOZ
R23 IOZ
U25 IOZ
T23 IOZ
U24 IOZ
T22 IOZ
R21 IOZ
U22 IOZ
U23 IOZ
V23 IOZ
U21 IOZ
T21 IOZ
V22 IOZ
W21 IOZ
V21 IOZ
AD20 I
Up
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
Down
AD18 I
AE19 I
A22 I
B22 I
AD14 I
AE15 I
C25 I
B25 I
Y15 P
F20 P
AA19 OZ
G2 OZ
H1 I
G4 I
F1
I
J5
I
G5 I
J4
I
H4 I
Y18 I
H5 O
H3 OZ
Down
Up
Up
Up
Up
Down
Down
Up
Up
Up
Down
F15 A
DESCRIPTION
Boot Configuration Pins
Endian configuration pin (Pin shared with GPIO[0])
See Section 6.24 for more details
(Pins shared with GPIO[1:13])
PCIe Mode selection pins (Pins shared with GPIO[14:15]) (Reserved for C6652)
PCIe module enable (Pin shared with TIMI0 and GPIO16) (Reserved for C6652)
Clock / Reset
Core Clock Input to main PLL.
DDR Reference Clock Input to DDR PLL
PCIe Clock Input to drive PCIe SerDes (Reserved for C6652)
Reserved
SYS_CLK PLL Power Supply Pin
DDR_CLK PLL Power Supply Pin
System Clock Output to be used as a general purpose output clock for debug
purposes
Interrupt output pulse created by IPCGRH
Nonmaskable Interrupt
Warm Reset
Enable for core selects
Select for the target core for LRESET and NMI. For more details see Table 5-8.
Full Reset
Warm Reset of non isolated portion on the IC
Power-on Reset
Reset Status Output
Boot progress indication output
PTV Compensation NMOS Reference Input. A precision resistor placed between the
PTV15 pin and ground is used to closely tune the output impedance of the DDR
interface drivers to 50 Ω. Presently, the recommended value for this 1% resistor is
45.3 Ω.
18
Terminal Configuration and Functions
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