TLC320AD57 Datasheet, PDF (9/21 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

2 Detailed Description
The following sections contain a detailed description of the TLC320AD57C.
2.1 Power-Down and Reset Functions
The following sections contain descriptions of the power-down and reset functions of the TLC320AD57C.
2.1.1 Power Down
The power-down state is comprised of a separate digital and analog power down. The power consumption
of each is detailed in Section 3.3, Electrical Characteristics.
The digital power-down mode shuts down the digital filters and clock generators. All digital outputs are set
to an unasserted level. When the digital power-down terminal (DigPD) is pulled low, normal operation of the
device is initiated.
In slave mode, the conversion process must synchronize to an input on the LRClk terminal and the SCLK
terminal. Therefore, the conversion process is not initiated until the first rising edges on both SCLK and
LRClk are detected after DigPD is pulled low. This synchronizes the conversion cycle. All conversions are
performed at a fixed LRClk rate [MCLK /256 (CMODE low) or MCLK /384 (CMODE high)] after the initial
synchronization. After the digital power-down terminal is brought low, the output of the digital filters remains
invalid for 50 LRClk cycles [see Figures 2–1(a) and 2–1(b)].
In master mode, LRClk is an output; therefore, the conversion process initiates based on internal timing.
The first valid data out occurs as shown in Figure 2–1(c).
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid, which renders the outputs of the digital filters invalid. When the analog power-down terminal is
brought low, the modulators are brought back online; however, the outputs of the digital filters require 50
LRClk cycles for valid results.
2–1